[lld] [llvm] [AArch64][ELF] Section alignment of 4 for AArch64 instruction (PR #114031)
Florin Popa via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 19 23:23:51 PST 2025
https://github.com/popaflorin updated https://github.com/llvm/llvm-project/pull/114031
>From cd58fa65328b648fa8894e66f3bcb7ec5515de33 Mon Sep 17 00:00:00 2001
From: Florin Popa <florin.popa at arm.com>
Date: Tue, 29 Oct 2024 10:43:25 +0000
Subject: [PATCH 1/8] [AArch64][ELF] Section alignment of 4 for AArch64
instruction
The integrated assembler sets a minimum alignment for the .text section of 4. However user defined sections get an alignment of 1. Unlike the GNU assembler which raises the section alignment to 4 if an AArch64 instruction is used, the integrated assembler leaves the alignment at 1
---
llvm/lib/MC/MCParser/ELFAsmParser.cpp | 9 ++++++++
.../directive-arch-section-alignment.s | 22 +++++++++++++++++++
2 files changed, 31 insertions(+)
create mode 100644 llvm/test/MC/AArch64/directive-arch-section-alignment.s
diff --git a/llvm/lib/MC/MCParser/ELFAsmParser.cpp b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
index 99b13c68a9966..978823359b17f 100644
--- a/llvm/lib/MC/MCParser/ELFAsmParser.cpp
+++ b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
@@ -700,6 +700,15 @@ bool ELFAsmParser::parseSectionArguments(bool IsPush, SMLoc loc) {
getContext().getELFSection(SectionName, Type, Flags, Size, GroupName,
IsComdat, UniqueID, LinkedToSym);
getStreamer().switchSection(Section, Subsection);
+
+ // Section alignment of 4 if an AArch64 instruction is used when $x mapping
+ // symbol is added Match GNU Assembler
+ const Triple &TT = getContext().getTargetTriple();
+ if ((Section->getFlags() & ELF::SHF_EXECINSTR) && (TT.isAArch64())) {
+ if (Section->getAlign() < 4)
+ getStreamer().emitValueToAlignment(Align(4));
+ }
+
// Check that flags are used consistently. However, the GNU assembler permits
// to leave out in subsequent uses of the same sections; for compatibility,
// do likewise.
diff --git a/llvm/test/MC/AArch64/directive-arch-section-alignment.s b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
new file mode 100644
index 0000000000000..bf3881b9c288a
--- /dev/null
+++ b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
@@ -0,0 +1,22 @@
+// RUN: llvm-mc -triple aarch64-- -o - %s | FileCheck %s
+
+// CHECK: .section sec00
+// CHECK-NEXT: .p2align 2
+// CHECK-NEXT: nop
+.section sec00, "ax"
+nop
+nop
+// CHECK: .section sec01
+// CHECK-NEXT: .p2align 2
+// CHECK-NEXT: .p2align 2
+// CHECK-NEXT: nop
+.section sec01, "ax"
+.balign 4
+nop
+// CHECK: .section sec02
+// CHECK-NEXT: .p2align 2
+// CHECK-NEXT: .byte 1
+.section sec02, "ax"
+// CHECK-NEXT: nop
+.byte 1
+nop
>From 00922f4b7c5aa1dc3eb76393d8602069371db8ab Mon Sep 17 00:00:00 2001
From: Florin Popa <florin.popa at arm.com>
Date: Tue, 29 Oct 2024 10:43:25 +0000
Subject: [PATCH 2/8] [AArch64][ELF] Section alignment of 4 for AArch64
instruction
The integrated assembler sets a minimum alignment for the .text section of 4. However user defined sections get an alignment of 1. Unlike the GNU assembler which raises the section alignment to 4 if an AArch64 instruction is used, the integrated assembler leaves the alignment at 1
---
llvm/lib/MC/MCParser/ELFAsmParser.cpp | 8 ------
.../MCTargetDesc/AArch64ELFStreamer.cpp | 6 +++++
.../directive-arch-section-alignment.s | 27 +++++++++----------
3 files changed, 19 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/MC/MCParser/ELFAsmParser.cpp b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
index 978823359b17f..b3653c7e5c5ed 100644
--- a/llvm/lib/MC/MCParser/ELFAsmParser.cpp
+++ b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
@@ -701,14 +701,6 @@ bool ELFAsmParser::parseSectionArguments(bool IsPush, SMLoc loc) {
IsComdat, UniqueID, LinkedToSym);
getStreamer().switchSection(Section, Subsection);
- // Section alignment of 4 if an AArch64 instruction is used when $x mapping
- // symbol is added Match GNU Assembler
- const Triple &TT = getContext().getTargetTriple();
- if ((Section->getFlags() & ELF::SHF_EXECINSTR) && (TT.isAArch64())) {
- if (Section->getAlign() < 4)
- getStreamer().emitValueToAlignment(Align(4));
- }
-
// Check that flags are used consistently. However, the GNU assembler permits
// to leave out in subsequent uses of the same sections; for compatibility,
// do likewise.
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
index d29d383bc2312..9e6114a80a21b 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
@@ -325,6 +325,12 @@ class AArch64ELFStreamer : public MCELFStreamer {
LastEMS = EMS_None;
MCELFStreamer::changeSection(Section, Subsection);
+
+ // Section alignment of 4 to match GNU Assembler
+ if (Section->getAlign() < 4) {
+ Section->setAlignment(Align(4));
+ emitValueToAlignment(Align(4), 0, 1, 0);
+ }
}
// Reset state between object emissions
diff --git a/llvm/test/MC/AArch64/directive-arch-section-alignment.s b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
index bf3881b9c288a..0c483a8817b20 100644
--- a/llvm/test/MC/AArch64/directive-arch-section-alignment.s
+++ b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
@@ -1,22 +1,21 @@
-// RUN: llvm-mc -triple aarch64-- -o - %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-windows -filetype obj -o %t.obj %s
+// RUN: llvm-objdump -d -r %t.obj | FileCheck %s
-// CHECK: .section sec00
-// CHECK-NEXT: .p2align 2
-// CHECK-NEXT: nop
.section sec00, "ax"
nop
nop
-// CHECK: .section sec01
-// CHECK-NEXT: .p2align 2
-// CHECK-NEXT: .p2align 2
-// CHECK-NEXT: nop
+nop
.section sec01, "ax"
.balign 4
nop
-// CHECK: .section sec02
-// CHECK-NEXT: .p2align 2
-// CHECK-NEXT: .byte 1
-.section sec02, "ax"
-// CHECK-NEXT: nop
-.byte 1
nop
+nop
+
+// CHECK: 0000000000000000 <sec00>:
+// CHECK-NEXT: 0: d503201f nop
+// CHECK-NEXT: 4: d503201f nop
+// CHECK-NEXT: 8: d503201f nop
+// CHECK: 0000000000000000 <sec01>:
+// CHECK-NEXT: 0: d503201f nop
+// CHECK-NEXT: 4: d503201f nop
+// CHECK-NEXT: 8: d503201f nop
>From 262d8cf6cc83a4d32a2c9bda92f862846d25eeab Mon Sep 17 00:00:00 2001
From: Florin Popa <florin.popa at arm.com>
Date: Tue, 29 Oct 2024 10:43:25 +0000
Subject: [PATCH 3/8] [AArch64][ELF] Section alignment of 4 for AArch64
instruction
The integrated assembler sets a minimum alignment for the .text section of 4. However user defined sections get an alignment of 1. Unlike the GNU assembler which raises the section alignment to 4 if an AArch64 instruction is used, the integrated assembler leaves the alignment at 1
---
llvm/lib/MC/MCParser/ELFAsmParser.cpp | 1 -
.../MCTargetDesc/AArch64ELFStreamer.cpp | 2 +-
.../directive-arch-section-alignment.s | 47 ++++++++++++++-----
3 files changed, 36 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/MC/MCParser/ELFAsmParser.cpp b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
index b3653c7e5c5ed..99b13c68a9966 100644
--- a/llvm/lib/MC/MCParser/ELFAsmParser.cpp
+++ b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
@@ -700,7 +700,6 @@ bool ELFAsmParser::parseSectionArguments(bool IsPush, SMLoc loc) {
getContext().getELFSection(SectionName, Type, Flags, Size, GroupName,
IsComdat, UniqueID, LinkedToSym);
getStreamer().switchSection(Section, Subsection);
-
// Check that flags are used consistently. However, the GNU assembler permits
// to leave out in subsequent uses of the same sections; for compatibility,
// do likewise.
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
index 9e6114a80a21b..fbeabe12997b4 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
@@ -327,7 +327,7 @@ class AArch64ELFStreamer : public MCELFStreamer {
MCELFStreamer::changeSection(Section, Subsection);
// Section alignment of 4 to match GNU Assembler
- if (Section->getAlign() < 4) {
+ if ((Section->getAlign() < 4) && Section->isText()) {
Section->setAlignment(Align(4));
emitValueToAlignment(Align(4), 0, 1, 0);
}
diff --git a/llvm/test/MC/AArch64/directive-arch-section-alignment.s b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
index 0c483a8817b20..4c83d65db8629 100644
--- a/llvm/test/MC/AArch64/directive-arch-section-alignment.s
+++ b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
@@ -1,21 +1,44 @@
-// RUN: llvm-mc -triple aarch64-windows -filetype obj -o %t.obj %s
-// RUN: llvm-objdump -d -r %t.obj | FileCheck %s
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj -o %t.obj %s
+// RUN: llvm-readobj -S --sd %t.obj | FileCheck %s --check-prefix=CHECK-OBJ
+// RUN: llvm-readelf -s %t.obj | FileCheck %s --check-prefix=CHECK-ELF
.section sec00, "ax"
+.byte 1
+.section sec01, "ax"
nop
nop
-nop
-.section sec01, "ax"
+.section sec02, "ax"
.balign 4
nop
nop
+.section sec03, "ax"
+.byte 0
+.section sec04, "aw"
nop
+nop
+
+// CHECK-OBJ: Name: sec00
+// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
+// CHECK-OBJ-NEXT: Flags [ (0x6)
+// CHECK-OBJ: AddressAlignment: 4
+// CHECK-OBJ: Name: sec01
+// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
+// CHECK-OBJ-NEXT: Flags [ (0x6)
+// CHECK-OBJ: AddressAlignment: 4
+// CHECK-OBJ: Name: sec02
+// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
+// CHECK-OBJ-NEXT: Flags [ (0x6)
+// CHECK-OBJ: Name: sec03
+// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
+// CHECK-OBJ-NEXT: Flags [ (0x6)
+// CHECK-OBJ: AddressAlignment: 4
+// CHECK-OBJ: Name: sec04
+// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
+// CHECK-OBJ-NEXT: Flags [ (0x3)
+// CHECK-OBJ: AddressAlignment: 1
-// CHECK: 0000000000000000 <sec00>:
-// CHECK-NEXT: 0: d503201f nop
-// CHECK-NEXT: 4: d503201f nop
-// CHECK-NEXT: 8: d503201f nop
-// CHECK: 0000000000000000 <sec01>:
-// CHECK-NEXT: 0: d503201f nop
-// CHECK-NEXT: 4: d503201f nop
-// CHECK-NEXT: 8: d503201f nop
+//CHECK-ELF: sec00 PROGBITS 0000000000000000 000040 000001 00 AX 0 0 4
+//CHECK-ELF-NEXT: sec01 PROGBITS 0000000000000000 000044 000008 00 AX 0 0 4
+//CHECK-ELF-NEXT: sec02 PROGBITS 0000000000000000 00004c 000008 00 AX 0 0 4
+//CHECK-ELF-NEXT: sec03 PROGBITS 0000000000000000 000054 000001 00 AX 0 0 4
+//CHECK-ELF-NEXT: sec04 PROGBITS 0000000000000000 000055 000008 00 WA 0 0 1
>From 471a0433713b2ae78aec04d2db469f4ccb5d809c Mon Sep 17 00:00:00 2001
From: Florin Popa <florin.popa at arm.com>
Date: Tue, 29 Oct 2024 10:43:25 +0000
Subject: [PATCH 4/8] [AArch64][ELF] Section alignment of 4 for AArch64
instruction
The integrated assembler sets a minimum alignment for the .text section of 4. However user defined sections get an alignment of 1. Unlike the GNU assembler which raises the section alignment to 4 if an AArch64 instruction is used, the integrated assembler leaves the alignment at 1
---
llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
index fbeabe12997b4..4d889d8daefa2 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
@@ -329,7 +329,6 @@ class AArch64ELFStreamer : public MCELFStreamer {
// Section alignment of 4 to match GNU Assembler
if ((Section->getAlign() < 4) && Section->isText()) {
Section->setAlignment(Align(4));
- emitValueToAlignment(Align(4), 0, 1, 0);
}
}
>From 18fbf0a440cd4e2680522c698ddac87df26f01ac Mon Sep 17 00:00:00 2001
From: Florin Popa <florin.popa at arm.com>
Date: Tue, 29 Oct 2024 10:43:25 +0000
Subject: [PATCH 5/8] [AArch64][ELF] Section alignment of 4 for AArch64
instruction
The integrated assembler sets a minimum alignment for the .text section of 4. However user defined sections get an alignment of 1. Unlike the GNU assembler which raises the section alignment to 4 if an AArch64 instruction is used, the integrated assembler leaves the alignment at 1
---
.../MCTargetDesc/AArch64ELFStreamer.cpp | 3 +-
.../directive-arch-section-alignment.s | 38 ++++++-------------
2 files changed, 12 insertions(+), 29 deletions(-)
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
index 4d889d8daefa2..e4c07fef9da0b 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
@@ -327,9 +327,8 @@ class AArch64ELFStreamer : public MCELFStreamer {
MCELFStreamer::changeSection(Section, Subsection);
// Section alignment of 4 to match GNU Assembler
- if ((Section->getAlign() < 4) && Section->isText()) {
+ if ((Section->getAlign() < 4) && Section->isText())
Section->setAlignment(Align(4));
- }
}
// Reset state between object emissions
diff --git a/llvm/test/MC/AArch64/directive-arch-section-alignment.s b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
index 4c83d65db8629..8b3be4e322cc1 100644
--- a/llvm/test/MC/AArch64/directive-arch-section-alignment.s
+++ b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
@@ -1,6 +1,5 @@
// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj -o %t.obj %s
-// RUN: llvm-readobj -S --sd %t.obj | FileCheck %s --check-prefix=CHECK-OBJ
-// RUN: llvm-readelf -s %t.obj | FileCheck %s --check-prefix=CHECK-ELF
+// RUN: llvm-readobj -S --sd %t.obj | FileCheck %s
.section sec00, "ax"
.byte 1
@@ -17,28 +16,13 @@ nop
nop
nop
-// CHECK-OBJ: Name: sec00
-// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
-// CHECK-OBJ-NEXT: Flags [ (0x6)
-// CHECK-OBJ: AddressAlignment: 4
-// CHECK-OBJ: Name: sec01
-// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
-// CHECK-OBJ-NEXT: Flags [ (0x6)
-// CHECK-OBJ: AddressAlignment: 4
-// CHECK-OBJ: Name: sec02
-// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
-// CHECK-OBJ-NEXT: Flags [ (0x6)
-// CHECK-OBJ: Name: sec03
-// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
-// CHECK-OBJ-NEXT: Flags [ (0x6)
-// CHECK-OBJ: AddressAlignment: 4
-// CHECK-OBJ: Name: sec04
-// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
-// CHECK-OBJ-NEXT: Flags [ (0x3)
-// CHECK-OBJ: AddressAlignment: 1
-
-//CHECK-ELF: sec00 PROGBITS 0000000000000000 000040 000001 00 AX 0 0 4
-//CHECK-ELF-NEXT: sec01 PROGBITS 0000000000000000 000044 000008 00 AX 0 0 4
-//CHECK-ELF-NEXT: sec02 PROGBITS 0000000000000000 00004c 000008 00 AX 0 0 4
-//CHECK-ELF-NEXT: sec03 PROGBITS 0000000000000000 000054 000001 00 AX 0 0 4
-//CHECK-ELF-NEXT: sec04 PROGBITS 0000000000000000 000055 000008 00 WA 0 0 1
+// CHECK: Name: sec00
+// CHECK: AddressAlignment: 4
+// CHECK: Name: sec01
+// CHECK: AddressAlignment: 4
+// CHECK: Name: sec02
+// CHECK: AddressAlignment: 4
+// CHECK: Name: sec03
+// CHECK: AddressAlignment: 4
+// CHECK: Name: sec04
+// CHECK: AddressAlignment: 1
\ No newline at end of file
>From 2aa199fb9e4e42ccea0d4a3817c3b6a85f03b5a6 Mon Sep 17 00:00:00 2001
From: Florin Popa <florin.popa at arm.com>
Date: Wed, 19 Feb 2025 11:18:25 +0000
Subject: [PATCH 6/8] [AArch64][ELF] Updated the synthax and fixed the lld test
As a result of review feedback, updated the synthax for the change and
first attempt to fix lld test that was failing due to missalignment
---
lld/test/ELF/aarch64-relocs.s | 17 +++++++++--------
.../AArch64/MCTargetDesc/AArch64ELFStreamer.cpp | 4 ++--
.../AArch64/directive-arch-section-alignment.s | 12 ++++++++----
3 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/lld/test/ELF/aarch64-relocs.s b/lld/test/ELF/aarch64-relocs.s
index 39cfcdd38661d..266380a88bddf 100644
--- a/lld/test/ELF/aarch64-relocs.s
+++ b/lld/test/ELF/aarch64-relocs.s
@@ -42,7 +42,7 @@ mystr:
# CHECK: Disassembly of section .R_AARCH64_ADD_ABS_LO12_NC:
# CHECK-EMPTY:
# CHECK-NEXT: <.R_AARCH64_ADD_ABS_LO12_NC>:
-# CHECK-NEXT: 21013b: 9104fc00 add x0, x0, #319
+# CHECK-NEXT: 210140: 91051000 add x0, x0, #324
.section .R_AARCH64_LDST64_ABS_LO12_NC,"ax", at progbits
ldr x28, [x27, :lo12:foo]
@@ -56,7 +56,7 @@ foo:
# CHECK: Disassembly of section .R_AARCH64_LDST64_ABS_LO12_NC:
# CHECK-EMPTY:
# CHECK-NEXT: <.R_AARCH64_LDST64_ABS_LO12_NC>:
-# CHECK-NEXT: 210144: f940a77c ldr x28, [x27, #328]
+# CHECK-NEXT: 21014c: f940ab7c ldr x28, [x27, #336]
.section .SUB,"ax", at progbits
nop
@@ -86,7 +86,7 @@ foo32:
# CHECK: Disassembly of section .R_AARCH64_LDST32_ABS_LO12_NC:
# CHECK-EMPTY:
# CHECK-NEXT: <ldst32>:
-# CHECK-NEXT: 21015c: bd4160a4 ldr s4, [x5, #352]
+# CHECK-NEXT: 210164: bd4168a4 ldr s4, [x5, #360]
.section .R_AARCH64_LDST8_ABS_LO12_NC,"ax", at progbits
ldst8:
@@ -101,11 +101,12 @@ foo8:
# CHECK: Disassembly of section .R_AARCH64_LDST8_ABS_LO12_NC:
# CHECK-EMPTY:
# CHECK-NEXT: <ldst8>:
-# CHECK-NEXT: 210164: 3985a1ab ldrsb x11, [x13, #360]
+# CHECK-NEXT: 21016c: 3985c1ab ldrsb x11, [x13, #368]
.section .R_AARCH64_LDST128_ABS_LO12_NC,"ax", at progbits
ldst128:
ldr q20, [x19, #:lo12:foo128]
+ .balign 16
foo128:
.asciz "foo"
.size mystr, 3
@@ -116,7 +117,7 @@ foo128:
# CHECK: Disassembly of section .R_AARCH64_LDST128_ABS_LO12_NC:
# CHECK-EMPTY:
# CHECK: <ldst128>:
-# CHECK: 21016c: 3dc05e74 ldr q20, [x19, #368]
+# CHECK: 210180: 3dc06674 ldr q20, [x19, #400]
#foo128:
# 210170: 66 6f 6f 00 .word
@@ -135,9 +136,9 @@ foo16:
# CHECK: Disassembly of section .R_AARCH64_LDST16_ABS_LO12_NC:
# CHECK-EMPTY:
# CHECK-NEXT: <ldst16>:
-# CHECK-NEXT: 210174: 7d430271 ldr h17, [x19, #384]
-# CHECK-NEXT: 210178: 79430261 ldrh w1, [x19, #384]
-# CHECK-NEXT: 21017c: 79430662 ldrh w2, [x19, #386]
+# CHECK-NEXT: 210194: 7d434271 ldr h17, [x19, #416]
+# CHECK-NEXT: 210198: 79434261 ldrh w1, [x19, #416]
+# CHECK-NEXT: 21019c: 79434662 ldrh w2, [x19, #418]
.section .R_AARCH64_MOVW_UABS,"ax", at progbits
movz1:
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
index e4c07fef9da0b..af64fceaa507e 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
@@ -327,8 +327,8 @@ class AArch64ELFStreamer : public MCELFStreamer {
MCELFStreamer::changeSection(Section, Subsection);
// Section alignment of 4 to match GNU Assembler
- if ((Section->getAlign() < 4) && Section->isText())
- Section->setAlignment(Align(4));
+ if (Section->isText())
+ Section->ensureMinAlignment(Align(4));
}
// Reset state between object emissions
diff --git a/llvm/test/MC/AArch64/directive-arch-section-alignment.s b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
index 8b3be4e322cc1..c8209a55acd50 100644
--- a/llvm/test/MC/AArch64/directive-arch-section-alignment.s
+++ b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
@@ -1,6 +1,5 @@
// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj -o %t.obj %s
// RUN: llvm-readobj -S --sd %t.obj | FileCheck %s
-
.section sec00, "ax"
.byte 1
.section sec01, "ax"
@@ -11,11 +10,14 @@ nop
nop
nop
.section sec03, "ax"
+.balign 8
+nop
+nop
+.section sec04, "ax"
.byte 0
-.section sec04, "aw"
+.section sec05, "aw"
nop
nop
-
// CHECK: Name: sec00
// CHECK: AddressAlignment: 4
// CHECK: Name: sec01
@@ -23,6 +25,8 @@ nop
// CHECK: Name: sec02
// CHECK: AddressAlignment: 4
// CHECK: Name: sec03
-// CHECK: AddressAlignment: 4
+// CHECK: AddressAlignment: 8
// CHECK: Name: sec04
+// CHECK: AddressAlignment: 4
+// CHECK: Name: sec05
// CHECK: AddressAlignment: 1
\ No newline at end of file
>From 1483be73573a8f10cf26d4e1dcfc64b2cc0aaf42 Mon Sep 17 00:00:00 2001
From: Florin Popa <florin.popa at arm.com>
Date: Wed, 19 Feb 2025 11:18:25 +0000
Subject: [PATCH 7/8] [AArch64][ELF] Updated the synthax and fixed the lld test
As a result of review feedback, updated the synthax for the change and
first attempt to fix lld test that was failing due to missalignment
---
lld/test/ELF/aarch64-relocs.s | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/lld/test/ELF/aarch64-relocs.s b/lld/test/ELF/aarch64-relocs.s
index 266380a88bddf..143b0fc56bf29 100644
--- a/lld/test/ELF/aarch64-relocs.s
+++ b/lld/test/ELF/aarch64-relocs.s
@@ -111,15 +111,16 @@ foo128:
.asciz "foo"
.size mystr, 3
-# S = 0x21016c, A = 0x4
-# R = ((S + A) & 0xFF8) << 6 = 0x00005c00
-# 0x00005c00 | 0x3dc00274 = 0x3dc05e74
+# S = 210180, A = 0x4
+# R = ((S + A) & 0xFF8) << 6 = 0x00006000
+# 0x00006000 | 0x3dc00274 = 0x3dc06274
# CHECK: Disassembly of section .R_AARCH64_LDST128_ABS_LO12_NC:
# CHECK-EMPTY:
# CHECK: <ldst128>:
# CHECK: 210180: 3dc06674 ldr q20, [x19, #400]
#foo128:
-# 210170: 66 6f 6f 00 .word
+# CHECK: <foo128>:
+# CHECK-NEXT: 210190: 66 6f 6f 00 .word
.section .R_AARCH64_LDST16_ABS_LO12_NC,"ax", at progbits
ldst16:
>From 83c8656808c33ecfc738917da178e03946bb8118 Mon Sep 17 00:00:00 2001
From: Florin Popa <florin.popa at arm.com>
Date: Thu, 20 Feb 2025 07:22:13 +0000
Subject: [PATCH 8/8] [AArch64][ELF] Renamed and updated the target for the
test
Renamed the test to align-code.s and changed generic aarch64 ELF
---
.../{directive-arch-section-alignment.s => align-code.s} | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
rename llvm/test/MC/AArch64/{directive-arch-section-alignment.s => align-code.s} (80%)
diff --git a/llvm/test/MC/AArch64/directive-arch-section-alignment.s b/llvm/test/MC/AArch64/align-code.s
similarity index 80%
rename from llvm/test/MC/AArch64/directive-arch-section-alignment.s
rename to llvm/test/MC/AArch64/align-code.s
index c8209a55acd50..d9bbb268d2242 100644
--- a/llvm/test/MC/AArch64/directive-arch-section-alignment.s
+++ b/llvm/test/MC/AArch64/align-code.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj -o %t.obj %s
-// RUN: llvm-readobj -S --sd %t.obj | FileCheck %s
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -o %t.o %s
+// RUN: llvm-readobj -S --sd %t.o | FileCheck %s
.section sec00, "ax"
.byte 1
.section sec01, "ax"
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