[llvm] [X86][NFC] Added/Updated Trigonometric functions testcases (PR #127094)
Evgenii Kudriashov via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 19 16:52:37 PST 2025
================
@@ -1188,3 +1188,422 @@ define void @test_half_trunc(half %a0, ptr %p0) nounwind {
store half %res, ptr %p0, align 2
ret void
}
+
+define half @use_acosf16(half %a) nounwind {
+; F16C-LABEL: use_acosf16:
+; F16C: # %bb.0:
+; F16C-NEXT: pushq %rax
+; F16C-NEXT: vcvtph2ps %xmm0, %xmm0
+; F16C-NEXT: callq acosf at PLT
+; F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0
+; F16C-NEXT: popq %rax
+; F16C-NEXT: retq
+;
+; FP16-LABEL: use_acosf16:
+; FP16: # %bb.0:
+; FP16-NEXT: pushq %rax
+; FP16-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; FP16-NEXT: callq acosf at PLT
+; FP16-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
+; FP16-NEXT: popq %rax
+; FP16-NEXT: retq
+;
+; X64-LABEL: use_acosf16:
+; X64: # %bb.0:
+; X64-NEXT: pushq %rax
+; X64-NEXT: callq __extendhfsf2 at PLT
+; X64-NEXT: callq acosf at PLT
+; X64-NEXT: callq __truncsfhf2 at PLT
+; X64-NEXT: popq %rax
+; X64-NEXT: retq
+;
+; X86-LABEL: use_acosf16:
+; X86: # %bb.0:
+; X86-NEXT: subl $12, %esp
+; X86-NEXT: pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT: pextrw $0, %xmm0, %eax
+; X86-NEXT: movw %ax, (%esp)
+; X86-NEXT: calll __extendhfsf2
+; X86-NEXT: fstps (%esp)
+; X86-NEXT: calll acosf
+; X86-NEXT: fstps (%esp)
+; X86-NEXT: calll __truncsfhf2
+; X86-NEXT: addl $12, %esp
+; X86-NEXT: retl
+ %x = call half @llvm.acos.f16(half %a)
+ ret half %x
+}
+
+define half @use_asinf16(half %a) nounwind {
+; F16C-LABEL: use_asinf16:
+; F16C: # %bb.0:
+; F16C-NEXT: pushq %rax
+; F16C-NEXT: vcvtph2ps %xmm0, %xmm0
+; F16C-NEXT: callq asinf at PLT
+; F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0
+; F16C-NEXT: popq %rax
+; F16C-NEXT: retq
+;
+; FP16-LABEL: use_asinf16:
+; FP16: # %bb.0:
+; FP16-NEXT: pushq %rax
+; FP16-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; FP16-NEXT: callq asinf at PLT
+; FP16-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
+; FP16-NEXT: popq %rax
+; FP16-NEXT: retq
+;
+; X64-LABEL: use_asinf16:
+; X64: # %bb.0:
+; X64-NEXT: pushq %rax
+; X64-NEXT: callq __extendhfsf2 at PLT
+; X64-NEXT: callq asinf at PLT
+; X64-NEXT: callq __truncsfhf2 at PLT
+; X64-NEXT: popq %rax
+; X64-NEXT: retq
+;
+; X86-LABEL: use_asinf16:
+; X86: # %bb.0:
+; X86-NEXT: subl $12, %esp
+; X86-NEXT: pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT: pextrw $0, %xmm0, %eax
+; X86-NEXT: movw %ax, (%esp)
+; X86-NEXT: calll __extendhfsf2
+; X86-NEXT: fstps (%esp)
+; X86-NEXT: calll asinf
+; X86-NEXT: fstps (%esp)
+; X86-NEXT: calll __truncsfhf2
+; X86-NEXT: addl $12, %esp
+; X86-NEXT: retl
+ %x = call half @llvm.asin.f16(half %a)
+ ret half %x
+}
+
+define half @use_atanf16(half %a) nounwind {
+; F16C-LABEL: use_atanf16:
+; F16C: # %bb.0:
+; F16C-NEXT: pushq %rax
+; F16C-NEXT: vcvtph2ps %xmm0, %xmm0
+; F16C-NEXT: callq atanf at PLT
+; F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0
+; F16C-NEXT: popq %rax
+; F16C-NEXT: retq
+;
+; FP16-LABEL: use_atanf16:
+; FP16: # %bb.0:
+; FP16-NEXT: pushq %rax
+; FP16-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; FP16-NEXT: callq atanf at PLT
+; FP16-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
+; FP16-NEXT: popq %rax
+; FP16-NEXT: retq
+;
+; X64-LABEL: use_atanf16:
+; X64: # %bb.0:
+; X64-NEXT: pushq %rax
+; X64-NEXT: callq __extendhfsf2 at PLT
+; X64-NEXT: callq atanf at PLT
+; X64-NEXT: callq __truncsfhf2 at PLT
+; X64-NEXT: popq %rax
+; X64-NEXT: retq
+;
+; X86-LABEL: use_atanf16:
+; X86: # %bb.0:
+; X86-NEXT: subl $12, %esp
+; X86-NEXT: pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT: pextrw $0, %xmm0, %eax
+; X86-NEXT: movw %ax, (%esp)
+; X86-NEXT: calll __extendhfsf2
+; X86-NEXT: fstps (%esp)
+; X86-NEXT: calll atanf
+; X86-NEXT: fstps (%esp)
+; X86-NEXT: calll __truncsfhf2
+; X86-NEXT: addl $12, %esp
+; X86-NEXT: retl
+ %x = call half @llvm.atan.f16(half %a)
+ ret half %x
+}
+
+define half @use_atan2f16(half %a, half %b) nounwind {
+; F16C-LABEL: use_atan2f16:
+; F16C: # %bb.0:
+; F16C-NEXT: pushq %rax
+; F16C-NEXT: vcvtph2ps %xmm0, %xmm0
+; F16C-NEXT: vcvtph2ps %xmm1, %xmm1
+; F16C-NEXT: callq atan2f at PLT
+; F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0
+; F16C-NEXT: popq %rax
+; F16C-NEXT: retq
+;
+; FP16-LABEL: use_atan2f16:
+; FP16: # %bb.0:
+; FP16-NEXT: pushq %rax
+; FP16-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; FP16-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
+; FP16-NEXT: callq atan2f at PLT
+; FP16-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
+; FP16-NEXT: popq %rax
+; FP16-NEXT: retq
+;
+; X64-LABEL: use_atan2f16:
+; X64: # %bb.0:
+; X64-NEXT: pushq %rax
+; X64-NEXT: movss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; X64-NEXT: movaps %xmm1, %xmm0
+; X64-NEXT: callq __extendhfsf2 at PLT
+; X64-NEXT: movss %xmm0, (%rsp) # 4-byte Spill
+; X64-NEXT: movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
+; X64-NEXT: # xmm0 = mem[0],zero,zero,zero
+; X64-NEXT: callq __extendhfsf2 at PLT
+; X64-NEXT: movss (%rsp), %xmm1 # 4-byte Reload
+; X64-NEXT: # xmm1 = mem[0],zero,zero,zero
+; X64-NEXT: callq atan2f at PLT
+; X64-NEXT: callq __truncsfhf2 at PLT
+; X64-NEXT: popq %rax
+; X64-NEXT: retq
+;
+; X86-LABEL: use_atan2f16:
+; X86: # %bb.0:
+; X86-NEXT: subl $60, %esp
+; X86-NEXT: pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT: movdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; X86-NEXT: pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT: pextrw $0, %xmm0, %eax
+; X86-NEXT: movw %ax, (%esp)
+; X86-NEXT: calll __extendhfsf2
+; X86-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill
+; X86-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; X86-NEXT: pextrw $0, %xmm0, %eax
+; X86-NEXT: movw %ax, (%esp)
+; X86-NEXT: calll __extendhfsf2
+; X86-NEXT: fstps {{[0-9]+}}(%esp)
+; X86-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
+; X86-NEXT: fstps (%esp)
+; X86-NEXT: calll atan2f
+; X86-NEXT: fstps (%esp)
+; X86-NEXT: calll __truncsfhf2
+; X86-NEXT: addl $60, %esp
+; X86-NEXT: retl
+ %x = call half @llvm.atan2.f16(half %a, half %b)
+ ret half %x
+}
+
+define float @test_cos_f32(float %Val) nounwind {
+; F16C-LABEL: test_cos_f32:
+; F16C: # %bb.0:
+; F16C-NEXT: jmp cosf at PLT # TAILCALL
+;
+; FP16-LABEL: test_cos_f32:
+; FP16: # %bb.0:
+; FP16-NEXT: jmp cosf at PLT # TAILCALL
+;
+; X64-LABEL: test_cos_f32:
+; X64: # %bb.0:
+; X64-NEXT: jmp cosf at PLT # TAILCALL
+;
+; X86-LABEL: test_cos_f32:
+; X86: # %bb.0:
+; X86-NEXT: jmp cosf # TAILCALL
+ %res = call float @llvm.cos.f32(float %Val)
+ ret float %res
+}
+
+define half @use_coshf16(half %a) nounwind {
+; F16C-LABEL: use_coshf16:
+; F16C: # %bb.0:
+; F16C-NEXT: pushq %rax
+; F16C-NEXT: vcvtph2ps %xmm0, %xmm0
+; F16C-NEXT: callq coshf at PLT
+; F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0
+; F16C-NEXT: popq %rax
+; F16C-NEXT: retq
+;
+; FP16-LABEL: use_coshf16:
+; FP16: # %bb.0:
+; FP16-NEXT: pushq %rax
+; FP16-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
+; FP16-NEXT: callq coshf at PLT
+; FP16-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
+; FP16-NEXT: popq %rax
+; FP16-NEXT: retq
+;
+; X64-LABEL: use_coshf16:
+; X64: # %bb.0:
+; X64-NEXT: pushq %rax
+; X64-NEXT: callq __extendhfsf2 at PLT
+; X64-NEXT: callq coshf at PLT
+; X64-NEXT: callq __truncsfhf2 at PLT
+; X64-NEXT: popq %rax
+; X64-NEXT: retq
+;
+; X86-LABEL: use_coshf16:
+; X86: # %bb.0:
+; X86-NEXT: subl $12, %esp
+; X86-NEXT: pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT: pextrw $0, %xmm0, %eax
+; X86-NEXT: movw %ax, (%esp)
+; X86-NEXT: calll __extendhfsf2
+; X86-NEXT: fstps (%esp)
+; X86-NEXT: calll coshf
+; X86-NEXT: fstps (%esp)
+; X86-NEXT: calll __truncsfhf2
+; X86-NEXT: addl $12, %esp
+; X86-NEXT: retl
+ %x = call half @llvm.cosh.f16(half %a)
+ ret half %x
+}
+
+define float @test_sin_f32(float %Val) nounwind {
+; F16C-LABEL: test_sin_f32:
+; F16C: # %bb.0:
+; F16C-NEXT: jmp sinf at PLT # TAILCALL
+;
+; FP16-LABEL: test_sin_f32:
+; FP16: # %bb.0:
+; FP16-NEXT: jmp sinf at PLT # TAILCALL
+;
+; X64-LABEL: test_sin_f32:
+; X64: # %bb.0:
+; X64-NEXT: jmp sinf at PLT # TAILCALL
+;
+; X86-LABEL: test_sin_f32:
+; X86: # %bb.0:
+; X86-NEXT: jmp sinf # TAILCALL
+ %res = call float @llvm.sin.f32(float %Val)
----------------
e-kud wrote:
ditto
https://github.com/llvm/llvm-project/pull/127094
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