[llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)

[Ricardo Jesus via llvm-commits]

rj-jesus wrote:

> From the output I see a NEON fadd, presumably because an existing combine looks through the insert subvector. If this is want you want to generate then my AArch64LoadStoreOpt suggestion will not work because it'll bypass the necessary combine.

I think the NEON FADD isn't critical to have - I'd be happy with an SVE FADD too, ideally unpredicated, which I do see emitted with the separate patch for SVE LDR/STR.

> If you're happy to limit the output changes to just the loads and stores then experimenting with emitting SVE fill/spill instruction and extending AArch64LoadStoreOpt would be nice because it could also optimise real spill/fill code. This would be especially beneficial across function calls.

That sounds good, in that case I'll put up a separate patch for the SVE LDR/STR case and separately experiment with the AArch64LoadStoreOpt alternative. In the meantime I'll also address your comments here, I just haven't had the chance to do so today (I'm sorry).

>  However, given this specifically relates to the ACLE, can the combine be restricted to pre type-legalisation? I think that'll cover your use case whilst removing the potential conflicts I'm worried about.

I think that should work, in fact I believe I tried that in an earlier version of the patch and I seem to recall it working.

https://github.com/llvm/llvm-project/pull/127500