[llvm] [GlobalISel] Introduce `G_POISON` (PR #127825)
Mateusz Sokół via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 19 08:23:20 PST 2025
https://github.com/mtsokol created https://github.com/llvm/llvm-project/pull/127825
Addresses #127486
Hi @arsenm,
Here's a WIP PR for visibility, so far I managed to introduce `G_POISON` and duplicate/mimic some of the `G_IMPLICIT_DEF` behavior (draft changes for sure). One test already runs with `llc` call up to `irtranslator` stage in `calllowering-nocrashret.ll` test.
I'm still missing legalization, as my tests fail with `unable to legalize instruction: G_POISON`, so I need a bit more time to get a better grasp of it.
>From 48adc0702b7649ba74ed6c405565137cc7b7c95d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Mateusz=20Sok=C3=B3=C5=82?= <mat646 at gmail.com>
Date: Wed, 19 Feb 2025 16:02:55 +0000
Subject: [PATCH] [GlobalISel] Introduce `G_POISON`
---
llvm/docs/GlobalISel/GenericOpcode.rst | 9 ++
.../llvm/CodeGen/GlobalISel/CombinerHelper.h | 17 ++++
.../CodeGen/GlobalISel/GenericMachineInstrs.h | 8 ++
.../CodeGen/GlobalISel/MachineIRBuilder.h | 5 +-
llvm/include/llvm/Support/TargetOpcodes.def | 5 +-
llvm/include/llvm/Target/GenericOpcodes.td | 6 ++
.../include/llvm/Target/GlobalISel/Combine.td | 93 ++++++++++++++-----
llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp | 3 +-
.../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 43 ++++++++-
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 +
.../GlobalISel/LegacyLegalizerInfo.cpp | 2 +
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 7 +-
.../GlobalISel/LostDebugLocObserver.cpp | 1 +
.../CodeGen/GlobalISel/MachineIRBuilder.cpp | 4 +
llvm/lib/CodeGen/GlobalISel/Utils.cpp | 10 +-
llvm/lib/CodeGen/MachineSSAContext.cpp | 3 +-
.../X86/GlobalISel/calllowering-nocrashret.ll | 15 ++-
.../GlobalISelEmitter/GlobalISelEmitter.td | 2 +-
18 files changed, 200 insertions(+), 35 deletions(-)
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index 8b76a407c34f8..fcffb78c8fc07 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -24,6 +24,15 @@ An undefined value.
%0:_(s32) = G_IMPLICIT_DEF
+G_POISON
+^^^^^^^^
+
+A poison value.
+
+.. code-block:: none
+
+ %0:_(s32) = G_POISON
+
G_CONSTANT
^^^^^^^^^^
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
index 9b78342c8fc39..1f0f30d1e5e85 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
@@ -431,16 +431,27 @@ class CombinerHelper {
/// G_IMPLICIT_DEF.
bool matchAnyExplicitUseIsUndef(MachineInstr &MI) const;
+ /// Return true if any explicit use operand on \p MI is defined by a
+ /// G_POISON.
+ bool matchAnyExplicitUseIsPoison(MachineInstr &MI) const;
+
/// Return true if all register explicit use operands on \p MI are defined by
/// a G_IMPLICIT_DEF.
bool matchAllExplicitUsesAreUndef(MachineInstr &MI) const;
+ /// Return true if all register explicit use operands on \p MI are defined by
+ /// a G_POISON.
+ bool matchAllExplicitUsesArePoison(MachineInstr &MI) const;
+
/// Return true if a G_SHUFFLE_VECTOR instruction \p MI has an undef mask.
bool matchUndefShuffleVectorMask(MachineInstr &MI) const;
/// Return true if a G_STORE instruction \p MI is storing an undef value.
bool matchUndefStore(MachineInstr &MI) const;
+ /// Return true if a G_STORE instruction \p MI is storing a poison value.
+ bool matchPoisonStore(MachineInstr &MI) const;
+
/// Return true if a G_SELECT instruction \p MI has an undef comparison.
bool matchUndefSelectCmp(MachineInstr &MI) const;
@@ -466,6 +477,9 @@ class CombinerHelper {
/// Replace an instruction with a G_IMPLICIT_DEF.
void replaceInstWithUndef(MachineInstr &MI) const;
+ /// Replace an instruction with a G_POISON.
+ void replaceInstWithPoison(MachineInstr &MI) const;
+
/// Delete \p MI and replace all of its uses with its \p OpIdx-th operand.
void replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx) const;
@@ -506,6 +520,9 @@ class CombinerHelper {
/// Check if operand \p OpIdx is undef.
bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx) const;
+ /// Check if operand \p OpIdx is poison.
+ bool matchOperandIsPoison(MachineInstr &MI, unsigned OpIdx) const;
+
/// Check if operand \p OpIdx is known to be a power of 2.
bool matchOperandIsKnownToBeAPowerOfTwo(MachineInstr &MI,
unsigned OpIdx) const;
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
index 9e5d4d34f24d2..ddcff441cea3b 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
@@ -343,6 +343,14 @@ class GImplicitDef : public GenericMachineInstr {
}
};
+/// Represents a G_POISON.
+class GPoison : public GenericMachineInstr {
+public:
+ static bool classof(const MachineInstr *MI) {
+ return MI->getOpcode() == TargetOpcode::G_POISON;
+ }
+};
+
/// Represents a G_SELECT.
class GSelect : public GenericMachineInstr {
public:
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 7b0475ac2481d..68399c93a9364 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1017,9 +1017,12 @@ class MachineIRBuilder {
/// \return a MachineInstrBuilder for the newly created instruction.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
- /// Build and insert \p Res = IMPLICIT_DEF.
+ /// Build and insert \p Res = G_IMPLICIT_DEF.
MachineInstrBuilder buildUndef(const DstOp &Res);
+ /// Build and insert \p Res = G_POISON.
+ MachineInstrBuilder buildPoison(const DstOp &Res);
+
/// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
///
/// G_MERGE_VALUES combines the input elements contiguously into a larger
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 5ef3707b81fe9..0170ac327c855 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -295,9 +295,12 @@ HANDLE_TARGET_OPCODE(G_ABDS)
/// Generic absolute difference unsigned instruction.
HANDLE_TARGET_OPCODE(G_ABDU)
-
+// Generic implicit definition.
HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF)
+// Generic poison value.
+HANDLE_TARGET_OPCODE(G_POISON)
+
/// Generic PHI instruction with types.
HANDLE_TARGET_OPCODE(G_PHI)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index e134bab61bf63..5b71641854eac 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -92,6 +92,12 @@ def G_IMPLICIT_DEF : GenericInstruction {
let hasSideEffects = false;
}
+def G_POISON : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins);
+ let hasSideEffects = false;
+}
+
def G_PHI : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins variable_ops);
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 3590ab221ad44..cb7ba26ce57ca 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -430,6 +430,12 @@ def binop_right_undef_to_undef: GICombineRule<
[{ return Helper.matchOperandIsUndef(*${root}, 2); }]),
(apply [{ Helper.replaceInstWithUndef(*${root}); }])>;
+def binop_right_poison_to_poison
+ : GICombineRule<(defs root:$root),
+ (match(wip_match_opcode G_SHL, G_ASHR, G_LSHR):$root,
+ [{ return Helper.matchOperandIsPoison(*${root}, 2); }]),
+ (apply [{ Helper.replaceInstWithPoison(*${root}); }])>;
+
def unary_undef_to_zero: GICombineRule<
(defs root:$root),
(match (wip_match_opcode G_ABS):$root,
@@ -447,6 +453,17 @@ def unary_undef_to_undef : GICombineRule<
(match (unary_undef_to_undef_frags $dst)),
(apply [{ Helper.replaceInstWithUndef(*${dst}.getParent()); }])>;
+def unary_poison_to_poison_frags
+ : GICombinePatFrag<(outs root:$dst), (ins),
+ !foreach(op,
+ [G_TRUNC, G_BITCAST, G_ANYEXT, G_PTRTOINT,
+ G_INTTOPTR, G_FPTOSI, G_FPTOUI],
+ (pattern(op $dst, $x), (G_POISON $x)))>;
+def unary_poison_to_poison
+ : GICombineRule<
+ (defs root:$dst), (match(unary_poison_to_poison_frags $dst)),
+ (apply [{ Helper.replaceInstWithPoison(*${dst}.getParent()); }])>;
+
// Instructions where if any source operand is undef, the instruction can be
// replaced with undef.
def propagate_undef_any_op: GICombineRule<
@@ -455,6 +472,15 @@ def propagate_undef_any_op: GICombineRule<
[{ return Helper.matchAnyExplicitUseIsUndef(*${root}); }]),
(apply [{ Helper.replaceInstWithUndef(*${root}); }])>;
+// Instructions where if any source operand is poison, the instruction can be
+// replaced with poison.
+def propagate_poison_any_op
+ : GICombineRule<
+ (defs root:$root),
+ (match(wip_match_opcode G_ADD, G_SUB, G_XOR):$root,
+ [{ return Helper.matchAnyExplicitUseIsPoison(*${root}); }]),
+ (apply [{ Helper.replaceInstWithPoison(*${root}); }])>;
+
// Instructions where if all source operands are undef, the instruction can be
// replaced with undef.
def propagate_undef_all_ops: GICombineRule<
@@ -463,6 +489,15 @@ def propagate_undef_all_ops: GICombineRule<
[{ return Helper.matchAllExplicitUsesAreUndef(*${root}); }]),
(apply [{ Helper.replaceInstWithUndef(*${root}); }])>;
+// Instructions where if all source operands are poison, the instruction can be
+// replaced with poison.
+def propagate_poison_all_ops
+ : GICombineRule<
+ (defs root:$root),
+ (match(wip_match_opcode G_SHUFFLE_VECTOR, G_BUILD_VECTOR):$root,
+ [{ return Helper.matchAllExplicitUsesArePoison(*${root}); }]),
+ (apply [{ Helper.replaceInstWithPoison(*${root}); }])>;
+
// Replace a G_SHUFFLE_VECTOR with an undef mask with a G_IMPLICIT_DEF.
def propagate_undef_shuffle_mask: GICombineRule<
(defs root:$root),
@@ -654,6 +689,13 @@ def erase_undef_store : GICombineRule<
(apply [{ Helper.eraseInst(*${root}); }])
>;
+// Erase stores of poison values.
+def erase_poison_store
+ : GICombineRule<(defs root:$root),
+ (match(wip_match_opcode G_STORE):$root,
+ [{ return Helper.matchPoisonStore(*${root}); }]),
+ (apply [{ Helper.eraseInst(*${root}); }])>;
+
def simplify_add_to_sub_matchinfo: GIDefMatchData<"std::tuple<Register, Register>">;
def simplify_add_to_sub: GICombineRule <
(defs root:$root, simplify_add_to_sub_matchinfo:$info),
@@ -1955,6 +1997,11 @@ def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
erase_undef_store,
insert_extract_vec_elt_out_of_bounds]>;
+def poison_combines
+ : GICombineGroup<[binop_right_poison_to_poison, unary_poison_to_poison,
+ propagate_poison_any_op, propagate_poison_all_ops,
+ erase_poison_store]>;
+
def identity_combines : GICombineGroup<[select_same_val, right_identity_zero,
binop_same_val, binop_left_to_zero,
binop_right_to_zero, p2i_to_i2p,
@@ -2006,29 +2053,29 @@ def shuffle_combines : GICombineGroup<[combine_shuffle_concat,
combine_shuffle_undef_rhs,
combine_shuffle_disjoint_mask]>;
-def all_combines : GICombineGroup<[integer_reassoc_combines, trivial_combines,
- vector_ops_combines, freeze_combines, cast_combines,
- insert_vec_elt_combines, extract_vec_elt_combines, combines_for_extload,
- combine_extracted_vector_load,
- undef_combines, identity_combines, phi_combines,
- simplify_add_to_sub, hoist_logic_op_with_same_opcode_hands, shifts_too_big,
- reassocs, ptr_add_immed_chain, cmp_combines,
- shl_ashr_to_sext_inreg, sext_inreg_of_load,
- width_reduction_combines, select_combines,
- known_bits_simplifications, trunc_shift,
- not_cmp_fold, opt_brcond_by_inverting_cond,
- const_combines, xor_of_and_with_same_reg, ptr_add_with_zero,
- shift_immed_chain, shift_of_shifted_logic_chain, load_or_combine,
- div_rem_to_divrem, funnel_shift_combines, bitreverse_shift, commute_shift,
- form_bitfield_extract, constant_fold_binops, constant_fold_fma,
- constant_fold_cast_op, fabs_fneg_fold,
- intdiv_combines, mulh_combines, redundant_neg_operands,
- and_or_disjoint_mask, fma_combines, fold_binop_into_select,
- sub_add_reg, select_to_minmax,
- fsub_to_fneg, commute_constant_to_rhs, match_ands, match_ors,
- simplify_neg_minmax, combine_concat_vector,
- sext_trunc, zext_trunc, prefer_sign_combines, shuffle_combines,
- combine_use_vector_truncate, merge_combines, overflow_combines]>;
+def all_combines
+ : GICombineGroup<
+ [integer_reassoc_combines, trivial_combines, vector_ops_combines,
+ freeze_combines, cast_combines, insert_vec_elt_combines,
+ extract_vec_elt_combines, combines_for_extload,
+ combine_extracted_vector_load, undef_combines, poison_combines,
+ identity_combines, phi_combines, simplify_add_to_sub,
+ hoist_logic_op_with_same_opcode_hands, shifts_too_big, reassocs,
+ ptr_add_immed_chain, cmp_combines, shl_ashr_to_sext_inreg,
+ sext_inreg_of_load, width_reduction_combines, select_combines,
+ known_bits_simplifications, trunc_shift, not_cmp_fold,
+ opt_brcond_by_inverting_cond, const_combines,
+ xor_of_and_with_same_reg, ptr_add_with_zero, shift_immed_chain,
+ shift_of_shifted_logic_chain, load_or_combine, div_rem_to_divrem,
+ funnel_shift_combines, bitreverse_shift, commute_shift,
+ form_bitfield_extract, constant_fold_binops, constant_fold_fma,
+ constant_fold_cast_op, fabs_fneg_fold, intdiv_combines,
+ mulh_combines, redundant_neg_operands, and_or_disjoint_mask,
+ fma_combines, fold_binop_into_select, sub_add_reg, select_to_minmax,
+ fsub_to_fneg, commute_constant_to_rhs, match_ands, match_ors,
+ simplify_neg_minmax, combine_concat_vector, sext_trunc, zext_trunc,
+ prefer_sign_combines, shuffle_combines, combine_use_vector_truncate,
+ merge_combines, overflow_combines]>;
// A combine group used to for prelegalizer combiners at -O0. The combines in
// this group have been selected based on experiments to balance code size and
diff --git a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
index 0222069cfc576..1e92856e7b647 100644
--- a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
@@ -54,6 +54,7 @@ bool CSEConfigFull::shouldCSEOpc(unsigned Opc) {
case TargetOpcode::G_CONSTANT:
case TargetOpcode::G_FCONSTANT:
case TargetOpcode::G_IMPLICIT_DEF:
+ case TargetOpcode::G_POISON:
case TargetOpcode::G_ZEXT:
case TargetOpcode::G_SEXT:
case TargetOpcode::G_ANYEXT:
@@ -82,7 +83,7 @@ bool CSEConfigFull::shouldCSEOpc(unsigned Opc) {
bool CSEConfigConstantOnly::shouldCSEOpc(unsigned Opc) {
return Opc == TargetOpcode::G_CONSTANT || Opc == TargetOpcode::G_FCONSTANT ||
- Opc == TargetOpcode::G_IMPLICIT_DEF;
+ Opc == TargetOpcode::G_IMPLICIT_DEF || Opc == TargetOpcode::G_POISON;
}
std::unique_ptr<CSEConfigBase>
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 0dfbb91f2ac54..73d7a572dabe6 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -328,6 +328,7 @@ bool CombinerHelper::matchCombineConcatVectors(
for (const MachineOperand &BuildVecMO : Def->uses())
Ops.push_back(BuildVecMO.getReg());
break;
+ case TargetOpcode::G_POISON:
case TargetOpcode::G_IMPLICIT_DEF: {
LLT OpType = MRI.getType(Reg);
// Keep one undef value for all the undef operands.
@@ -2695,6 +2696,12 @@ bool CombinerHelper::matchAnyExplicitUseIsUndef(MachineInstr &MI) const {
});
}
+bool CombinerHelper::matchAnyExplicitUseIsPoison(MachineInstr &MI) const {
+ return any_of(MI.explicit_uses(), [this](const MachineOperand &MO) {
+ return MO.isReg() && getOpcodeDef(TargetOpcode::G_POISON, MO.getReg(), MRI);
+ });
+}
+
bool CombinerHelper::matchAllExplicitUsesAreUndef(MachineInstr &MI) const {
return all_of(MI.explicit_uses(), [this](const MachineOperand &MO) {
return !MO.isReg() ||
@@ -2702,6 +2709,13 @@ bool CombinerHelper::matchAllExplicitUsesAreUndef(MachineInstr &MI) const {
});
}
+bool CombinerHelper::matchAllExplicitUsesArePoison(MachineInstr &MI) const {
+ return all_of(MI.explicit_uses(), [this](const MachineOperand &MO) {
+ return !MO.isReg() ||
+ getOpcodeDef(TargetOpcode::G_POISON, MO.getReg(), MRI);
+ });
+}
+
bool CombinerHelper::matchUndefShuffleVectorMask(MachineInstr &MI) const {
assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR);
ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask();
@@ -2714,6 +2728,11 @@ bool CombinerHelper::matchUndefStore(MachineInstr &MI) const {
MRI);
}
+bool CombinerHelper::matchPoisonStore(MachineInstr &MI) const {
+ assert(MI.getOpcode() == TargetOpcode::G_STORE);
+ return getOpcodeDef(TargetOpcode::G_POISON, MI.getOperand(0).getReg(), MRI);
+}
+
bool CombinerHelper::matchUndefSelectCmp(MachineInstr &MI) const {
assert(MI.getOpcode() == TargetOpcode::G_SELECT);
return getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(1).getReg(),
@@ -2953,6 +2972,12 @@ bool CombinerHelper::matchOperandIsUndef(MachineInstr &MI,
getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI);
}
+bool CombinerHelper::matchOperandIsPoison(MachineInstr &MI,
+ unsigned OpIdx) const {
+ MachineOperand &MO = MI.getOperand(OpIdx);
+ return MO.isReg() && getOpcodeDef(TargetOpcode::G_POISON, MO.getReg(), MRI);
+}
+
bool CombinerHelper::matchOperandIsKnownToBeAPowerOfTwo(MachineInstr &MI,
unsigned OpIdx) const {
MachineOperand &MO = MI.getOperand(OpIdx);
@@ -2992,6 +3017,12 @@ void CombinerHelper::replaceInstWithUndef(MachineInstr &MI) const {
MI.eraseFromParent();
}
+void CombinerHelper::replaceInstWithPoison(MachineInstr &MI) const {
+ assert(MI.getNumDefs() == 1 && "Expected only one def?");
+ Builder.buildPoison(MI.getOperand(0));
+ MI.eraseFromParent();
+}
+
bool CombinerHelper::matchSimplifyAddToSub(
MachineInstr &MI, std::tuple<Register, Register> &MatchInfo) const {
Register LHS = MI.getOperand(1).getReg();
@@ -3056,6 +3087,7 @@ bool CombinerHelper::matchCombineInsertVecElts(
// If we didn't end in a G_IMPLICIT_DEF and the source is not fully
// overwritten, bail out.
return TmpInst->getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
+ TmpInst->getOpcode() == TargetOpcode::G_POISON ||
all_of(MatchInfo, [](Register Reg) { return !!Reg; });
}
@@ -3426,12 +3458,13 @@ bool CombinerHelper::matchUseVectorTruncate(MachineInstr &MI,
if (I < 2)
return false;
- // Check the remaining source elements are only G_IMPLICIT_DEF
+ // Check the remaining source elements are only G_IMPLICIT_DEF or G_POISON
for (; I < NumOperands; ++I) {
auto SrcMI = MRI.getVRegDef(BuildMI->getSourceReg(I));
auto SrcMIOpc = SrcMI->getOpcode();
- if (SrcMIOpc != TargetOpcode::G_IMPLICIT_DEF)
+ if (SrcMIOpc != TargetOpcode::G_IMPLICIT_DEF &&
+ SrcMIOpc != TargetOpcode::G_POISON)
return false;
}
@@ -7892,6 +7925,12 @@ bool CombinerHelper::matchShuffleDisjointMask(MachineInstr &MI,
if (getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Shuffle.getSrc2Reg(), MRI))
return false;
+ if (getOpcodeDef(TargetOpcode::G_POISON, Shuffle.getSrc1Reg(), MRI))
+ return false;
+
+ if (getOpcodeDef(TargetOpcode::G_POISON, Shuffle.getSrc2Reg(), MRI))
+ return false;
+
const LLT DstTy = MRI.getType(Shuffle.getReg(0));
const LLT Src1Ty = MRI.getType(Shuffle.getSrc1Reg());
if (!isLegalOrBeforeLegalizer(
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index d01de29826cad..95eae9c8c4f3f 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -3660,6 +3660,8 @@ bool IRTranslator::translate(const Constant &C, Register Reg) {
EntryBuilder->buildConstant(Reg, *CI);
else if (auto CF = dyn_cast<ConstantFP>(&C))
EntryBuilder->buildFConstant(Reg, *CF);
+ else if (isa<PoisonValue>(C))
+ EntryBuilder->buildPoison(Reg);
else if (isa<UndefValue>(C))
EntryBuilder->buildUndef(Reg);
else if (isa<ConstantPointerNull>(C))
diff --git a/llvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp b/llvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp
index f338f66997657..bcc0760c7794e 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp
@@ -82,6 +82,8 @@ LegacyLegalizerInfo::LegacyLegalizerInfo() {
setLegalizeScalarToDifferentSizeStrategy(
TargetOpcode::G_IMPLICIT_DEF, 0, narrowToSmallerAndUnsupportedIfTooSmall);
+ setLegalizeScalarToDifferentSizeStrategy(
+ TargetOpcode::G_POISON, 0, narrowToSmallerAndUnsupportedIfTooSmall);
setLegalizeScalarToDifferentSizeStrategy(
TargetOpcode::G_ADD, 0, widenToLargerTypesAndNarrowToLargest);
setLegalizeScalarToDifferentSizeStrategy(
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index d4cb224c35d74..52d35134eec00 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -1425,6 +1425,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
switch (MI.getOpcode()) {
default:
return UnableToLegalize;
+ case TargetOpcode::G_POISON:
case TargetOpcode::G_IMPLICIT_DEF: {
Register DstReg = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(DstReg);
@@ -3082,6 +3083,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
MI.eraseFromParent();
return Legalized;
}
+ case TargetOpcode::G_POISON:
case TargetOpcode::G_IMPLICIT_DEF: {
Observer.changingInstr(MI);
widenScalarDst(MI, WideTy);
@@ -5308,6 +5310,7 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
switch (MI.getOpcode()) {
case G_IMPLICIT_DEF:
+ case G_POISON:
case G_TRUNC:
case G_AND:
case G_OR:
@@ -6048,6 +6051,7 @@ LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
LLT MoreTy) {
unsigned Opc = MI.getOpcode();
switch (Opc) {
+ case TargetOpcode::G_POISON:
case TargetOpcode::G_IMPLICIT_DEF:
case TargetOpcode::G_LOAD: {
if (TypeIdx != 0)
@@ -8450,7 +8454,8 @@ LegalizerHelper::lowerVECTOR_COMPRESS(llvm::MachineInstr &MI) {
auto OutPos = MIRBuilder.buildConstant(IdxTy, 0);
bool HasPassthru =
- MRI.getVRegDef(Passthru)->getOpcode() != TargetOpcode::G_IMPLICIT_DEF;
+ MRI.getVRegDef(Passthru)->getOpcode() != TargetOpcode::G_IMPLICIT_DEF &&
+ MRI.getVRegDef(Passthru)->getOpcode() != TargetOpcode::G_POISON;
if (HasPassthru)
MIRBuilder.buildStore(Passthru, StackPtr, PtrInfo, VecAlign);
diff --git a/llvm/lib/CodeGen/GlobalISel/LostDebugLocObserver.cpp b/llvm/lib/CodeGen/GlobalISel/LostDebugLocObserver.cpp
index 6d606e5550f1a..8c19dd39a4aa8 100644
--- a/llvm/lib/CodeGen/GlobalISel/LostDebugLocObserver.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LostDebugLocObserver.cpp
@@ -85,6 +85,7 @@ static bool irTranslatorNeverAddsLocations(unsigned Opcode) {
case TargetOpcode::G_CONSTANT:
case TargetOpcode::G_FCONSTANT:
case TargetOpcode::G_IMPLICIT_DEF:
+ case TargetOpcode::G_POISON:
case TargetOpcode::G_GLOBAL_VALUE:
return true;
}
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index db59ca1be281c..4d9b26117d512 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -642,6 +642,10 @@ MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
}
+MachineInstrBuilder MachineIRBuilder::buildPoison(const DstOp &Res) {
+ return buildInstr(TargetOpcode::G_POISON, {Res}, {});
+}
+
MachineInstrBuilder MachineIRBuilder::buildMergeValues(const DstOp &Res,
ArrayRef<Register> Ops) {
// Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index 625d556e3ff5e..373a427fb72a2 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -1470,6 +1470,7 @@ static bool isConstantScalar(const MachineInstr &MI,
switch (MI.getOpcode()) {
case TargetOpcode::G_CONSTANT:
case TargetOpcode::G_IMPLICIT_DEF:
+ case TargetOpcode::G_POISON:
return true;
case TargetOpcode::G_FCONSTANT:
return AllowFP;
@@ -1547,6 +1548,7 @@ llvm::isConstantOrConstantSplatVectorFP(MachineInstr &MI,
bool llvm::isNullOrNullSplat(const MachineInstr &MI,
const MachineRegisterInfo &MRI, bool AllowUndefs) {
switch (MI.getOpcode()) {
+ case TargetOpcode::G_POISON:
case TargetOpcode::G_IMPLICIT_DEF:
return AllowUndefs;
case TargetOpcode::G_CONSTANT:
@@ -1566,6 +1568,7 @@ bool llvm::isAllOnesOrAllOnesSplat(const MachineInstr &MI,
const MachineRegisterInfo &MRI,
bool AllowUndefs) {
switch (MI.getOpcode()) {
+ case TargetOpcode::G_POISON:
case TargetOpcode::G_IMPLICIT_DEF:
return AllowUndefs;
case TargetOpcode::G_CONSTANT:
@@ -1582,7 +1585,8 @@ bool llvm::matchUnaryPredicate(
std::function<bool(const Constant *ConstVal)> Match, bool AllowUndefs) {
const MachineInstr *Def = getDefIgnoringCopies(Reg, MRI);
- if (AllowUndefs && Def->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
+ if (AllowUndefs && (Def->getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
+ Def->getOpcode() == TargetOpcode::G_POISON))
return Match(nullptr);
// TODO: Also handle fconstant
@@ -1595,7 +1599,8 @@ bool llvm::matchUnaryPredicate(
for (unsigned I = 1, E = Def->getNumOperands(); I != E; ++I) {
Register SrcElt = Def->getOperand(I).getReg();
const MachineInstr *SrcDef = getDefIgnoringCopies(SrcElt, MRI);
- if (AllowUndefs && SrcDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
+ if (AllowUndefs && (Def->getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
+ Def->getOpcode() == TargetOpcode::G_POISON)) {
if (!Match(nullptr))
return false;
continue;
@@ -1914,6 +1919,7 @@ static bool isGuaranteedNotToBeUndefOrPoison(Register Reg,
switch (RegDef->getOpcode()) {
case TargetOpcode::G_FREEZE:
return true;
+ case TargetOpcode::G_POISON:
case TargetOpcode::G_IMPLICIT_DEF:
return !includesUndef(Kind);
case TargetOpcode::G_CONSTANT:
diff --git a/llvm/lib/CodeGen/MachineSSAContext.cpp b/llvm/lib/CodeGen/MachineSSAContext.cpp
index 8e13c0916dd9e..4b60edd103e65 100644
--- a/llvm/lib/CodeGen/MachineSSAContext.cpp
+++ b/llvm/lib/CodeGen/MachineSSAContext.cpp
@@ -56,7 +56,8 @@ const MachineBasicBlock *MachineSSAContext::getDefBlock(Register value) const {
static bool isUndef(const MachineInstr &MI) {
return MI.getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
- MI.getOpcode() == TargetOpcode::IMPLICIT_DEF;
+ MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
+ MI.getOpcode() == TargetOpcode::G_POISON;
}
/// MachineInstr equivalent of PHINode::hasConstantOrUndefValue() for G_PHI.
diff --git a/llvm/test/CodeGen/X86/GlobalISel/calllowering-nocrashret.ll b/llvm/test/CodeGen/X86/GlobalISel/calllowering-nocrashret.ll
index 5e9311559b400..74363203f8fca 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/calllowering-nocrashret.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/calllowering-nocrashret.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=x86_64-linux-gnu -o - -global-isel %s -stop-after=irtranslator | FileCheck %s
-define <4 x i1> @foo() {
- ; CHECK-LABEL: name: foo
+define <4 x i1> @foo_undef() {
+ ; CHECK-LABEL: name: foo_undef
; CHECK: bb.1.entry:
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s1>) = G_IMPLICIT_DEF
; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[DEF]](<4 x s1>)
@@ -11,3 +11,14 @@ define <4 x i1> @foo() {
entry:
ret <4 x i1> undef ;
}
+
+define <4 x i1> @foo_poison() {
+ ; CHECK-LABEL: name: foo_poison
+ ; CHECK: bb.1.entry:
+ ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s1>) = G_POISON
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[DEF]](<4 x s1>)
+ ; CHECK: $xmm0 = COPY [[ANYEXT]](<4 x s32>)
+ ; CHECK: RET 0, implicit $xmm0
+entry:
+ ret <4 x i1> poison ;
+}
diff --git a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
index b7132bf2bcd8c..d1c0e5d9d3105 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
@@ -513,7 +513,7 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
// R00O-NEXT: GIM_Reject,
// R00O: // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
// R00O-NEXT: GIM_Reject,
-// R00O-NEXT: }; // Size: 1840 bytes
+// R00O-NEXT: }; // Size: 1844 bytes
def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, GPR32:$src4),
[(set GPR32:$dst,
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