[lld] [llvm] [AArch64][ELF] Section alignment of 4 for AArch64 instruction (PR #114031)
Florin Popa via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 19 08:06:37 PST 2025
https://github.com/popaflorin updated https://github.com/llvm/llvm-project/pull/114031
>From f9e526c76673e3c4528d3b19eab81a91d2178593 Mon Sep 17 00:00:00 2001
From: Florin Popa <florin.popa at arm.com>
Date: Tue, 29 Oct 2024 10:43:25 +0000
Subject: [PATCH 1/7] [AArch64][ELF] Section alignment of 4 for AArch64
instruction
The integrated assembler sets a minimum alignment for the .text section of 4. However user defined sections get an alignment of 1. Unlike the GNU assembler which raises the section alignment to 4 if an AArch64 instruction is used, the integrated assembler leaves the alignment at 1
---
llvm/lib/MC/MCParser/ELFAsmParser.cpp | 9 ++++++++
.../directive-arch-section-alignment.s | 22 +++++++++++++++++++
2 files changed, 31 insertions(+)
create mode 100644 llvm/test/MC/AArch64/directive-arch-section-alignment.s
diff --git a/llvm/lib/MC/MCParser/ELFAsmParser.cpp b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
index c4536441665fa..8e7256d6fae9c 100644
--- a/llvm/lib/MC/MCParser/ELFAsmParser.cpp
+++ b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
@@ -697,6 +697,15 @@ bool ELFAsmParser::ParseSectionArguments(bool IsPush, SMLoc loc) {
getContext().getELFSection(SectionName, Type, Flags, Size, GroupName,
IsComdat, UniqueID, LinkedToSym);
getStreamer().switchSection(Section, Subsection);
+
+ // Section alignment of 4 if an AArch64 instruction is used when $x mapping
+ // symbol is added Match GNU Assembler
+ const Triple &TT = getContext().getTargetTriple();
+ if ((Section->getFlags() & ELF::SHF_EXECINSTR) && (TT.isAArch64())) {
+ if (Section->getAlign() < 4)
+ getStreamer().emitValueToAlignment(Align(4));
+ }
+
// Check that flags are used consistently. However, the GNU assembler permits
// to leave out in subsequent uses of the same sections; for compatibility,
// do likewise.
diff --git a/llvm/test/MC/AArch64/directive-arch-section-alignment.s b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
new file mode 100644
index 0000000000000..bf3881b9c288a
--- /dev/null
+++ b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
@@ -0,0 +1,22 @@
+// RUN: llvm-mc -triple aarch64-- -o - %s | FileCheck %s
+
+// CHECK: .section sec00
+// CHECK-NEXT: .p2align 2
+// CHECK-NEXT: nop
+.section sec00, "ax"
+nop
+nop
+// CHECK: .section sec01
+// CHECK-NEXT: .p2align 2
+// CHECK-NEXT: .p2align 2
+// CHECK-NEXT: nop
+.section sec01, "ax"
+.balign 4
+nop
+// CHECK: .section sec02
+// CHECK-NEXT: .p2align 2
+// CHECK-NEXT: .byte 1
+.section sec02, "ax"
+// CHECK-NEXT: nop
+.byte 1
+nop
>From beb10570240460c24f59cc3360afde67a61f5872 Mon Sep 17 00:00:00 2001
From: Florin Popa <florin.popa at arm.com>
Date: Tue, 29 Oct 2024 10:43:25 +0000
Subject: [PATCH 2/7] [AArch64][ELF] Section alignment of 4 for AArch64
instruction
The integrated assembler sets a minimum alignment for the .text section of 4. However user defined sections get an alignment of 1. Unlike the GNU assembler which raises the section alignment to 4 if an AArch64 instruction is used, the integrated assembler leaves the alignment at 1
---
llvm/lib/MC/MCParser/ELFAsmParser.cpp | 8 ------
.../MCTargetDesc/AArch64ELFStreamer.cpp | 6 +++++
.../directive-arch-section-alignment.s | 27 +++++++++----------
3 files changed, 19 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/MC/MCParser/ELFAsmParser.cpp b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
index 8e7256d6fae9c..67b043b51c62c 100644
--- a/llvm/lib/MC/MCParser/ELFAsmParser.cpp
+++ b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
@@ -698,14 +698,6 @@ bool ELFAsmParser::ParseSectionArguments(bool IsPush, SMLoc loc) {
IsComdat, UniqueID, LinkedToSym);
getStreamer().switchSection(Section, Subsection);
- // Section alignment of 4 if an AArch64 instruction is used when $x mapping
- // symbol is added Match GNU Assembler
- const Triple &TT = getContext().getTargetTriple();
- if ((Section->getFlags() & ELF::SHF_EXECINSTR) && (TT.isAArch64())) {
- if (Section->getAlign() < 4)
- getStreamer().emitValueToAlignment(Align(4));
- }
-
// Check that flags are used consistently. However, the GNU assembler permits
// to leave out in subsequent uses of the same sections; for compatibility,
// do likewise.
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
index 490efb650d503..e15a9237cda1d 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
@@ -202,6 +202,12 @@ class AArch64ELFStreamer : public MCELFStreamer {
LastEMS = EMS_None;
MCELFStreamer::changeSection(Section, Subsection);
+
+ // Section alignment of 4 to match GNU Assembler
+ if (Section->getAlign() < 4) {
+ Section->setAlignment(Align(4));
+ emitValueToAlignment(Align(4), 0, 1, 0);
+ }
}
// Reset state between object emissions
diff --git a/llvm/test/MC/AArch64/directive-arch-section-alignment.s b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
index bf3881b9c288a..0c483a8817b20 100644
--- a/llvm/test/MC/AArch64/directive-arch-section-alignment.s
+++ b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
@@ -1,22 +1,21 @@
-// RUN: llvm-mc -triple aarch64-- -o - %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-windows -filetype obj -o %t.obj %s
+// RUN: llvm-objdump -d -r %t.obj | FileCheck %s
-// CHECK: .section sec00
-// CHECK-NEXT: .p2align 2
-// CHECK-NEXT: nop
.section sec00, "ax"
nop
nop
-// CHECK: .section sec01
-// CHECK-NEXT: .p2align 2
-// CHECK-NEXT: .p2align 2
-// CHECK-NEXT: nop
+nop
.section sec01, "ax"
.balign 4
nop
-// CHECK: .section sec02
-// CHECK-NEXT: .p2align 2
-// CHECK-NEXT: .byte 1
-.section sec02, "ax"
-// CHECK-NEXT: nop
-.byte 1
nop
+nop
+
+// CHECK: 0000000000000000 <sec00>:
+// CHECK-NEXT: 0: d503201f nop
+// CHECK-NEXT: 4: d503201f nop
+// CHECK-NEXT: 8: d503201f nop
+// CHECK: 0000000000000000 <sec01>:
+// CHECK-NEXT: 0: d503201f nop
+// CHECK-NEXT: 4: d503201f nop
+// CHECK-NEXT: 8: d503201f nop
>From 5f7eb072ba8270334453d480d72a424bac568f6c Mon Sep 17 00:00:00 2001
From: Florin Popa <florin.popa at arm.com>
Date: Tue, 29 Oct 2024 10:43:25 +0000
Subject: [PATCH 3/7] [AArch64][ELF] Section alignment of 4 for AArch64
instruction
The integrated assembler sets a minimum alignment for the .text section of 4. However user defined sections get an alignment of 1. Unlike the GNU assembler which raises the section alignment to 4 if an AArch64 instruction is used, the integrated assembler leaves the alignment at 1
---
llvm/lib/MC/MCParser/ELFAsmParser.cpp | 1 -
.../MCTargetDesc/AArch64ELFStreamer.cpp | 2 +-
.../directive-arch-section-alignment.s | 47 ++++++++++++++-----
3 files changed, 36 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/MC/MCParser/ELFAsmParser.cpp b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
index 67b043b51c62c..c4536441665fa 100644
--- a/llvm/lib/MC/MCParser/ELFAsmParser.cpp
+++ b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
@@ -697,7 +697,6 @@ bool ELFAsmParser::ParseSectionArguments(bool IsPush, SMLoc loc) {
getContext().getELFSection(SectionName, Type, Flags, Size, GroupName,
IsComdat, UniqueID, LinkedToSym);
getStreamer().switchSection(Section, Subsection);
-
// Check that flags are used consistently. However, the GNU assembler permits
// to leave out in subsequent uses of the same sections; for compatibility,
// do likewise.
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
index e15a9237cda1d..0e4fb27718d46 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
@@ -204,7 +204,7 @@ class AArch64ELFStreamer : public MCELFStreamer {
MCELFStreamer::changeSection(Section, Subsection);
// Section alignment of 4 to match GNU Assembler
- if (Section->getAlign() < 4) {
+ if ((Section->getAlign() < 4) && Section->isText()) {
Section->setAlignment(Align(4));
emitValueToAlignment(Align(4), 0, 1, 0);
}
diff --git a/llvm/test/MC/AArch64/directive-arch-section-alignment.s b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
index 0c483a8817b20..4c83d65db8629 100644
--- a/llvm/test/MC/AArch64/directive-arch-section-alignment.s
+++ b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
@@ -1,21 +1,44 @@
-// RUN: llvm-mc -triple aarch64-windows -filetype obj -o %t.obj %s
-// RUN: llvm-objdump -d -r %t.obj | FileCheck %s
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj -o %t.obj %s
+// RUN: llvm-readobj -S --sd %t.obj | FileCheck %s --check-prefix=CHECK-OBJ
+// RUN: llvm-readelf -s %t.obj | FileCheck %s --check-prefix=CHECK-ELF
.section sec00, "ax"
+.byte 1
+.section sec01, "ax"
nop
nop
-nop
-.section sec01, "ax"
+.section sec02, "ax"
.balign 4
nop
nop
+.section sec03, "ax"
+.byte 0
+.section sec04, "aw"
nop
+nop
+
+// CHECK-OBJ: Name: sec00
+// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
+// CHECK-OBJ-NEXT: Flags [ (0x6)
+// CHECK-OBJ: AddressAlignment: 4
+// CHECK-OBJ: Name: sec01
+// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
+// CHECK-OBJ-NEXT: Flags [ (0x6)
+// CHECK-OBJ: AddressAlignment: 4
+// CHECK-OBJ: Name: sec02
+// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
+// CHECK-OBJ-NEXT: Flags [ (0x6)
+// CHECK-OBJ: Name: sec03
+// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
+// CHECK-OBJ-NEXT: Flags [ (0x6)
+// CHECK-OBJ: AddressAlignment: 4
+// CHECK-OBJ: Name: sec04
+// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
+// CHECK-OBJ-NEXT: Flags [ (0x3)
+// CHECK-OBJ: AddressAlignment: 1
-// CHECK: 0000000000000000 <sec00>:
-// CHECK-NEXT: 0: d503201f nop
-// CHECK-NEXT: 4: d503201f nop
-// CHECK-NEXT: 8: d503201f nop
-// CHECK: 0000000000000000 <sec01>:
-// CHECK-NEXT: 0: d503201f nop
-// CHECK-NEXT: 4: d503201f nop
-// CHECK-NEXT: 8: d503201f nop
+//CHECK-ELF: sec00 PROGBITS 0000000000000000 000040 000001 00 AX 0 0 4
+//CHECK-ELF-NEXT: sec01 PROGBITS 0000000000000000 000044 000008 00 AX 0 0 4
+//CHECK-ELF-NEXT: sec02 PROGBITS 0000000000000000 00004c 000008 00 AX 0 0 4
+//CHECK-ELF-NEXT: sec03 PROGBITS 0000000000000000 000054 000001 00 AX 0 0 4
+//CHECK-ELF-NEXT: sec04 PROGBITS 0000000000000000 000055 000008 00 WA 0 0 1
>From 46b0b4e970e70d6d881ba0f919ac30c51bf98e8a Mon Sep 17 00:00:00 2001
From: Florin Popa <florin.popa at arm.com>
Date: Tue, 29 Oct 2024 10:43:25 +0000
Subject: [PATCH 4/7] [AArch64][ELF] Section alignment of 4 for AArch64
instruction
The integrated assembler sets a minimum alignment for the .text section of 4. However user defined sections get an alignment of 1. Unlike the GNU assembler which raises the section alignment to 4 if an AArch64 instruction is used, the integrated assembler leaves the alignment at 1
---
llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
index 0e4fb27718d46..29de1a11600d0 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
@@ -206,7 +206,6 @@ class AArch64ELFStreamer : public MCELFStreamer {
// Section alignment of 4 to match GNU Assembler
if ((Section->getAlign() < 4) && Section->isText()) {
Section->setAlignment(Align(4));
- emitValueToAlignment(Align(4), 0, 1, 0);
}
}
>From 0a7346fea454e31e3d8d887555c28e23e3cfecea Mon Sep 17 00:00:00 2001
From: Florin Popa <florin.popa at arm.com>
Date: Tue, 29 Oct 2024 10:43:25 +0000
Subject: [PATCH 5/7] [AArch64][ELF] Section alignment of 4 for AArch64
instruction
The integrated assembler sets a minimum alignment for the .text section of 4. However user defined sections get an alignment of 1. Unlike the GNU assembler which raises the section alignment to 4 if an AArch64 instruction is used, the integrated assembler leaves the alignment at 1
---
.../MCTargetDesc/AArch64ELFStreamer.cpp | 3 +-
.../directive-arch-section-alignment.s | 38 ++++++-------------
2 files changed, 12 insertions(+), 29 deletions(-)
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
index 29de1a11600d0..0dc091e42755b 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
@@ -204,9 +204,8 @@ class AArch64ELFStreamer : public MCELFStreamer {
MCELFStreamer::changeSection(Section, Subsection);
// Section alignment of 4 to match GNU Assembler
- if ((Section->getAlign() < 4) && Section->isText()) {
+ if ((Section->getAlign() < 4) && Section->isText())
Section->setAlignment(Align(4));
- }
}
// Reset state between object emissions
diff --git a/llvm/test/MC/AArch64/directive-arch-section-alignment.s b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
index 4c83d65db8629..8b3be4e322cc1 100644
--- a/llvm/test/MC/AArch64/directive-arch-section-alignment.s
+++ b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
@@ -1,6 +1,5 @@
// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj -o %t.obj %s
-// RUN: llvm-readobj -S --sd %t.obj | FileCheck %s --check-prefix=CHECK-OBJ
-// RUN: llvm-readelf -s %t.obj | FileCheck %s --check-prefix=CHECK-ELF
+// RUN: llvm-readobj -S --sd %t.obj | FileCheck %s
.section sec00, "ax"
.byte 1
@@ -17,28 +16,13 @@ nop
nop
nop
-// CHECK-OBJ: Name: sec00
-// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
-// CHECK-OBJ-NEXT: Flags [ (0x6)
-// CHECK-OBJ: AddressAlignment: 4
-// CHECK-OBJ: Name: sec01
-// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
-// CHECK-OBJ-NEXT: Flags [ (0x6)
-// CHECK-OBJ: AddressAlignment: 4
-// CHECK-OBJ: Name: sec02
-// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
-// CHECK-OBJ-NEXT: Flags [ (0x6)
-// CHECK-OBJ: Name: sec03
-// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
-// CHECK-OBJ-NEXT: Flags [ (0x6)
-// CHECK-OBJ: AddressAlignment: 4
-// CHECK-OBJ: Name: sec04
-// CHECK-OBJ-NEXT: Type: SHT_PROGBITS (0x1)
-// CHECK-OBJ-NEXT: Flags [ (0x3)
-// CHECK-OBJ: AddressAlignment: 1
-
-//CHECK-ELF: sec00 PROGBITS 0000000000000000 000040 000001 00 AX 0 0 4
-//CHECK-ELF-NEXT: sec01 PROGBITS 0000000000000000 000044 000008 00 AX 0 0 4
-//CHECK-ELF-NEXT: sec02 PROGBITS 0000000000000000 00004c 000008 00 AX 0 0 4
-//CHECK-ELF-NEXT: sec03 PROGBITS 0000000000000000 000054 000001 00 AX 0 0 4
-//CHECK-ELF-NEXT: sec04 PROGBITS 0000000000000000 000055 000008 00 WA 0 0 1
+// CHECK: Name: sec00
+// CHECK: AddressAlignment: 4
+// CHECK: Name: sec01
+// CHECK: AddressAlignment: 4
+// CHECK: Name: sec02
+// CHECK: AddressAlignment: 4
+// CHECK: Name: sec03
+// CHECK: AddressAlignment: 4
+// CHECK: Name: sec04
+// CHECK: AddressAlignment: 1
\ No newline at end of file
>From 9e504766d50bed08377c2a53b8cc7a1a13f21b98 Mon Sep 17 00:00:00 2001
From: Florin Popa <florin.popa at arm.com>
Date: Wed, 19 Feb 2025 11:18:25 +0000
Subject: [PATCH 6/7] [AArch64][ELF] Updated the synthax and fixed the lld test
As a result of review feedback, updated the synthax for the change and
first attempt to fix lld test that was failing due to missalignment
---
lld/test/ELF/aarch64-relocs.s | 65 ++++++++++---------
.../MCTargetDesc/AArch64ELFStreamer.cpp | 4 +-
.../directive-arch-section-alignment.s | 12 ++--
3 files changed, 43 insertions(+), 38 deletions(-)
diff --git a/lld/test/ELF/aarch64-relocs.s b/lld/test/ELF/aarch64-relocs.s
index 198674c085b54..cfd64fd5e4804 100644
--- a/lld/test/ELF/aarch64-relocs.s
+++ b/lld/test/ELF/aarch64-relocs.s
@@ -30,7 +30,7 @@ mystr:
# CHECK: Disassembly of section .R_AARCH64_ADR_PREL_PG_HI21:
# CHECK-EMPTY:
# CHECK-NEXT: <.R_AARCH64_ADR_PREL_PG_HI21>:
-# CHECK-NEXT: 210132: 90000001 adrp x1, 0x210000
+# CHECK-NEXT: 210134: 90000001 adrp x1, 0x210000
.section .R_AARCH64_ADD_ABS_LO12_NC,"ax", at progbits
add x0, x0, :lo12:.L.str
@@ -44,7 +44,7 @@ mystr:
# CHECK: Disassembly of section .R_AARCH64_ADD_ABS_LO12_NC:
# CHECK-EMPTY:
# CHECK-NEXT: <.R_AARCH64_ADD_ABS_LO12_NC>:
-# CHECK-NEXT: 21013b: 9104fc00 add x0, x0, #319
+# CHECK-NEXT: 210140: 91051000 add x0, x0, #324
.section .R_AARCH64_LDST64_ABS_LO12_NC,"ax", at progbits
ldr x28, [x27, :lo12:foo]
@@ -58,7 +58,7 @@ foo:
# CHECK: Disassembly of section .R_AARCH64_LDST64_ABS_LO12_NC:
# CHECK-EMPTY:
# CHECK-NEXT: <.R_AARCH64_LDST64_ABS_LO12_NC>:
-# CHECK-NEXT: 210144: f940a77c ldr x28, [x27, #328]
+# CHECK-NEXT: 21014c: f940ab7c ldr x28, [x27, #336]
.section .SUB,"ax", at progbits
nop
@@ -68,9 +68,9 @@ sub:
# CHECK: Disassembly of section .SUB:
# CHECK-EMPTY:
# CHECK-NEXT: <.SUB>:
-# CHECK-NEXT: 21014c: d503201f nop
+# CHECK-NEXT: 210154: d503201f nop
# CHECK: <sub>:
-# CHECK-NEXT: 210150: d503201f nop
+# CHECK-NEXT: 210158: d503201f nop
.section .R_AARCH64_CALL26,"ax", at progbits
call26:
@@ -83,7 +83,7 @@ call26:
# CHECK: Disassembly of section .R_AARCH64_CALL26:
# CHECK-EMPTY:
# CHECK-NEXT: <call26>:
-# CHECK-NEXT: 210154: 97ffffff bl 0x210150
+# CHECK-NEXT: 21015c: 97ffffff bl 0x210158
.section .R_AARCH64_JUMP26,"ax", at progbits
jump26:
@@ -96,7 +96,7 @@ jump26:
# CHECK: Disassembly of section .R_AARCH64_JUMP26:
# CHECK-EMPTY:
# CHECK-NEXT: <jump26>:
-# CHECK-NEXT: 210158: 17fffffe b 0x210150
+# CHECK-NEXT: 210160: 17fffffe b 0x210158
.section .R_AARCH64_LDST32_ABS_LO12_NC,"ax", at progbits
ldst32:
@@ -111,7 +111,7 @@ foo32:
# CHECK: Disassembly of section .R_AARCH64_LDST32_ABS_LO12_NC:
# CHECK-EMPTY:
# CHECK-NEXT: <ldst32>:
-# CHECK-NEXT: 21015c: bd4160a4 ldr s4, [x5, #352]
+# CHECK-NEXT: 210164: bd4168a4 ldr s4, [x5, #360]
.section .R_AARCH64_LDST8_ABS_LO12_NC,"ax", at progbits
ldst8:
@@ -126,11 +126,12 @@ foo8:
# CHECK: Disassembly of section .R_AARCH64_LDST8_ABS_LO12_NC:
# CHECK-EMPTY:
# CHECK-NEXT: <ldst8>:
-# CHECK-NEXT: 210164: 3985a1ab ldrsb x11, [x13, #360]
+# CHECK-NEXT: 21016c: 3985c1ab ldrsb x11, [x13, #368]
.section .R_AARCH64_LDST128_ABS_LO12_NC,"ax", at progbits
ldst128:
ldr q20, [x19, #:lo12:foo128]
+ .balign 16
foo128:
.asciz "foo"
.size mystr, 3
@@ -141,7 +142,7 @@ foo128:
# CHECK: Disassembly of section .R_AARCH64_LDST128_ABS_LO12_NC:
# CHECK-EMPTY:
# CHECK: <ldst128>:
-# CHECK: 21016c: 3dc05e74 ldr q20, [x19, #368]
+# CHECK: 210180: 3dc06674 ldr q20, [x19, #400]
#foo128:
# 210170: 66 6f 6f 00 .word
@@ -160,9 +161,9 @@ foo16:
# CHECK: Disassembly of section .R_AARCH64_LDST16_ABS_LO12_NC:
# CHECK-EMPTY:
# CHECK-NEXT: <ldst16>:
-# CHECK-NEXT: 210174: 7d430271 ldr h17, [x19, #384]
-# CHECK-NEXT: 210178: 79430261 ldrh w1, [x19, #384]
-# CHECK-NEXT: 21017c: 79430662 ldrh w2, [x19, #386]
+# CHECK-NEXT: 210194: 7d434271 ldr h17, [x19, #416]
+# CHECK-NEXT: 210198: 79434261 ldrh w1, [x19, #416]
+# CHECK-NEXT: 21019c: 79434662 ldrh w2, [x19, #418]
.section .R_AARCH64_MOVW_UABS,"ax", at progbits
movz1:
@@ -199,8 +200,8 @@ movz1:
# CHECK: Disassembly of section .R_AARCH64_MOVW_SABS:
# CHECK-EMPTY:
# CHECK-NEXT: :
-# CHECK-NEXT: d2800021 mov x1, #1
-# CHECK-NEXT: 92800001 mov x1, #-1
+# CHECK-NEXT: d2800021 mov x1, #1
+# CHECK-NEXT: 92800001 mov x1, #-1
# CHECK-NEXT: d2a00042 mov x2, #131072
## -65537 = 0xfffffffffffeffff
# CHECK-NEXT: 92a00022 mov x2, #-65537
@@ -231,24 +232,24 @@ movz1:
# CHECK: Disassembly of section .R_AARCH64_MOVW_PREL:
# CHECK-EMPTY:
# CHECK-NEXT: :
-# CHECK-NEXT: 2101bc: d2800021 mov x1, #1
-# CHECK-NEXT: 2101c0: 92800001 mov x1, #-1
-# CHECK-NEXT: 2101c4: f2800021 movk x1, #1
-# CHECK-NEXT: 2101c8: f29fffe1 movk x1, #65535
-# CHECK-NEXT: 2101cc: d2a00042 mov x2, #131072
+# CHECK-NEXT: 2101dc: d2800021 mov x1, #1
+# CHECK-NEXT: 2101e0: 92800001 mov x1, #-1
+# CHECK-NEXT: 2101e4: f2800021 movk x1, #1
+# CHECK-NEXT: 2101e8: f29fffe1 movk x1, #65535
+# CHECK-NEXT: 2101ec: d2a00042 mov x2, #131072
## -65537 = 0xfffffffffffeffff
-# CHECK-NEXT: 2101d0: 92a00022 mov x2, #-65537
-# CHECK-NEXT: 2101d4: f2a00042 movk x2, #2, lsl #16
-# CHECK-NEXT: 2101d8: f2bfffc2 movk x2, #65534, lsl #16
+# CHECK-NEXT: 2101f0: 92a00022 mov x2, #-65537
+# CHECK-NEXT: 2101f4: f2a00042 movk x2, #2, lsl #16
+# CHECK-NEXT: 2101f8: f2bfffc2 movk x2, #65534, lsl #16
## 12884901888 = 0x300000000
-# CHECK-NEXT: 2101dc: d2c00063 mov x3, #12884901888
+# CHECK-NEXT: 2101fc: d2c00063 mov x3, #12884901888
## -8589934593 = #0xfffffffdffffffff
-# CHECK-NEXT: 2101e0: 92c00043 mov x3, #-8589934593
-# CHECK-NEXT: 2101e4: f2c00063 movk x3, #3, lsl #32
-# CHECK-NEXT: 2101e8: f2dfffa3 movk x3, #65533, lsl #32
-# CHECK-NEXT: 2101ec: d2c00063 mov x3, #12884901888
+# CHECK-NEXT: 210200: 92c00043 mov x3, #-8589934593
+# CHECK-NEXT: 210204: f2c00063 movk x3, #3, lsl #32
+# CHECK-NEXT: 210208: f2dfffa3 movk x3, #65533, lsl #32
+# CHECK-NEXT: 21020c: d2c00063 mov x3, #12884901888
## 1125899906842624 = 0x4000000000000
-# CHECK-NEXT: 2101f0: d2e00084 mov x4, #1125899906842624
-# CHECK-NEXT: 2101f4: d2ffff84 mov x4, #-1125899906842624
-# CHECK-NEXT: 2101f8: f2e00084 movk x4, #4, lsl #48
-# CHECK-NEXT: 2101fc: f2ffff84 movk x4, #65532, lsl #48
+# CHECK-NEXT: 210210: d2e00084 mov x4, #1125899906842624
+# CHECK-NEXT: 210214: d2ffff84 mov x4, #-1125899906842624
+# CHECK-NEXT: 210218: f2e00084 movk x4, #4, lsl #48
+# CHECK-NEXT: 21021c: f2ffff84 movk x4, #65532, lsl #48
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
index e4c07fef9da0b..af64fceaa507e 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
@@ -327,8 +327,8 @@ class AArch64ELFStreamer : public MCELFStreamer {
MCELFStreamer::changeSection(Section, Subsection);
// Section alignment of 4 to match GNU Assembler
- if ((Section->getAlign() < 4) && Section->isText())
- Section->setAlignment(Align(4));
+ if (Section->isText())
+ Section->ensureMinAlignment(Align(4));
}
// Reset state between object emissions
diff --git a/llvm/test/MC/AArch64/directive-arch-section-alignment.s b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
index 8b3be4e322cc1..c8209a55acd50 100644
--- a/llvm/test/MC/AArch64/directive-arch-section-alignment.s
+++ b/llvm/test/MC/AArch64/directive-arch-section-alignment.s
@@ -1,6 +1,5 @@
// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj -o %t.obj %s
// RUN: llvm-readobj -S --sd %t.obj | FileCheck %s
-
.section sec00, "ax"
.byte 1
.section sec01, "ax"
@@ -11,11 +10,14 @@ nop
nop
nop
.section sec03, "ax"
+.balign 8
+nop
+nop
+.section sec04, "ax"
.byte 0
-.section sec04, "aw"
+.section sec05, "aw"
nop
nop
-
// CHECK: Name: sec00
// CHECK: AddressAlignment: 4
// CHECK: Name: sec01
@@ -23,6 +25,8 @@ nop
// CHECK: Name: sec02
// CHECK: AddressAlignment: 4
// CHECK: Name: sec03
-// CHECK: AddressAlignment: 4
+// CHECK: AddressAlignment: 8
// CHECK: Name: sec04
+// CHECK: AddressAlignment: 4
+// CHECK: Name: sec05
// CHECK: AddressAlignment: 1
\ No newline at end of file
>From 4315325c1e73f8a567761ba2a1ff4d0f570df63e Mon Sep 17 00:00:00 2001
From: Florin Popa <florin.popa at arm.com>
Date: Wed, 19 Feb 2025 11:18:25 +0000
Subject: [PATCH 7/7] [AArch64][ELF] Updated the synthax and fixed the lld test
As a result of review feedback, updated the synthax for the change and
first attempt to fix lld test that was failing due to missalignment
---
lld/test/ELF/aarch64-relocs.s | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/lld/test/ELF/aarch64-relocs.s b/lld/test/ELF/aarch64-relocs.s
index cfd64fd5e4804..08bb33ac63dcb 100644
--- a/lld/test/ELF/aarch64-relocs.s
+++ b/lld/test/ELF/aarch64-relocs.s
@@ -136,15 +136,16 @@ foo128:
.asciz "foo"
.size mystr, 3
-# S = 0x21016c, A = 0x4
-# R = ((S + A) & 0xFF8) << 6 = 0x00005c00
-# 0x00005c00 | 0x3dc00274 = 0x3dc05e74
+# S = 210180, A = 0x4
+# R = ((S + A) & 0xFF8) << 6 = 0x00006000
+# 0x00006000 | 0x3dc00274 = 0x3dc06274
# CHECK: Disassembly of section .R_AARCH64_LDST128_ABS_LO12_NC:
# CHECK-EMPTY:
# CHECK: <ldst128>:
# CHECK: 210180: 3dc06674 ldr q20, [x19, #400]
#foo128:
-# 210170: 66 6f 6f 00 .word
+# CHECK: <foo128>:
+# CHECK-NEXT: 210190: 66 6f 6f 00 .word
.section .R_AARCH64_LDST16_ABS_LO12_NC,"ax", at progbits
ldst16:
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