[llvm] [PowerPC] Deprecate uses of ISD::ADDC/ISD::ADDE/ISD::SUBC/ISD::SUBE (PR #116984)
Kai Luo via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 19 07:27:16 PST 2025
bzEq wrote:
A potential fix for it
```
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 4720928f472b..f9159417e2a6 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -12059,7 +12059,7 @@ SDValue PPCTargetLowering::LowerADDSUBO(SDValue Op, SelectionDAG &DAG) const {
DAG, Subtarget);
if (!IsAdd)
Carry = DAG.getNode(ISD::XOR, DL, CarryType, Carry,
- DAG.getAllOnesConstant(DL, CarryType));
+ DAG.getConstant(1UL, DL, CarryType));
return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, Carry);
}
@@ -12075,7 +12075,7 @@ SDValue PPCTargetLowering::LowerADDSUBO_CARRY(SDValue Op,
Opc = IsAdd ? PPCISD::ADDE : PPCISD::SUBE;
if (!IsAdd)
CarryOp = DAG.getNode(ISD::XOR, DL, CarryOp.getValueType(), CarryOp,
- DAG.getAllOnesConstant(DL, CarryOp.getValueType()));
+ DAG.getConstant(1UL, DL, CarryOp.getValueType()));
CarryOp = ConvertCarryValueToCarryFlag(VT, CarryOp, DAG, Subtarget);
SDValue Sum = DAG.getNode(Opc, DL, DAG.getVTList(VT, MVT::i32),
Op.getOperand(0), Op.getOperand(1), CarryOp);
@@ -12083,7 +12083,7 @@ SDValue PPCTargetLowering::LowerADDSUBO_CARRY(SDValue Op,
Subtarget);
if (!IsAdd)
CarryOp = DAG.getNode(ISD::XOR, DL, CarryOp.getValueType(), CarryOp,
- DAG.getAllOnesConstant(DL, CarryOp.getValueType()));
+ DAG.getConstant(1UL, DL, CarryOp.getValueType()));
return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, CarryOp);
}
@@ -18329,7 +18329,7 @@ static SDValue combineADDToADDZE(SDNode *N, SelectionDAG &DAG,
DAG.getConstant(0, DL, MVT::i64), AddOrZ,
DAG.getConstant(0, DL, CarryType));
SDValue Invert = DAG.getNode(ISD::XOR, DL, CarryType, Subc.getValue(1),
- DAG.getAllOnesConstant(DL, CarryType));
+ DAG.getConstant(1UL, DL, CarryType));
return DAG.getNode(ISD::UADDO_CARRY, DL, VTs, LHS,
DAG.getConstant(0, DL, MVT::i64), Invert);
}
```
in addition to https://github.com/llvm/llvm-project/pull/127376.
https://github.com/llvm/llvm-project/pull/116984
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