[llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)

[Paul Walker via llvm-commits]

================
@@ -23550,6 +23550,31 @@ static SDValue combineV3I8LoadExt(LoadSDNode *LD, SelectionDAG &DAG) {
   return DAG.getMergeValues({Extract, TokenFactor}, DL);
 }
 
+// Replace scalable loads with fixed loads when vscale_range(1, 1).
+// This enables further optimisations such as LDP folds.
+static SDValue combineVScale1Load(LoadSDNode *LD, SelectionDAG &DAG,
+                                  const AArch64Subtarget *Subtarget) {
+  EVT MemVT = LD->getMemoryVT();
+  if (!Subtarget->isNeonAvailable() || !MemVT.isScalableVector() ||
----------------
paulwalker-arm wrote:

I think `hasNEON` should be enough here because the NEON load/store instruction remain available when in StreamingMode.

Should the combine be restricted to little endian only?

https://github.com/llvm/llvm-project/pull/127500