[llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)

Paul Walker via llvm-commits llvm-commits at lists.llvm.org
Wed Feb 19 04:09:49 PST 2025

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https://github.com/paulwalker-arm edited https://github.com/llvm/llvm-project/pull/127500

Previous message: [llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)
Next message: [llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)
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