[llvm] [RISCV] Move VMV0 elimination past machine SSA opts (PR #126850)

[Luke Lau via llvm-commits]

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@@ -1515,40 +1515,36 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64(<vscale x 16 x double> %va, <
 ; CHECK-NEXT:    vmv1r.v v0, v6
 ; CHECK-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
 ; CHECK-NEXT:    vfabs.v v24, v16, v0.t
+; CHECK-NEXT:    addi a2, sp, 16
+; CHECK-NEXT:    vs8r.v v24, (a2) # Unknown-size Folded Spill
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lukel97 wrote:

Yeah it's the same thing as this case here, definitely very weird: https://github.com/llvm/llvm-project/pull/126850#discussion_r1959584774

My main suspicion is that the physical COPYs to $v0 throw everything off, possible due to it assigning a register hint. I had a previous idea to rejig the vmv0 elimination pass to instead emit COPYs to vmv0 around the uses, instead of $v0, and see if the register allocator likes that better. I'll give it another shot.

FWIW these test cases with the weird spilling are very artificial (LMUL 16 types) and I would pray we never see them in the real world. 

https://github.com/llvm/llvm-project/pull/126850