[llvm] [NFC][AMDGPU] Pre-commit a test case for `v_pk_mov_b32` in `vgpr-remat.mir` (PR #127715)
Shilei Tian via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 18 20:39:43 PST 2025
https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/127715
>From e2460d1787cf7604d9618abf179ea0790044a455 Mon Sep 17 00:00:00 2001
From: Shilei Tian <i at tianshilei.me>
Date: Tue, 18 Feb 2025 18:10:44 -0500
Subject: [PATCH 1/3] [NFC][AMDGPU] Pre-commit a test case for `v_pk_mov_b32`
in `vgpr-remat.mir`
This PR serves as a preliminary step, adding a test case for `v_pk_mov_b32` in
`vgpr-remat.mir`. It is intended to demonstrate the code changes introduced in
an upcoming PR.
---
llvm/test/CodeGen/AMDGPU/vgpr-remat.mir | 47 +++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-remat.mir b/llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
index 08f5550f3b08a..0d4f779b53976 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
@@ -46,3 +46,50 @@ body: |
%4.sub1:vreg_96 = COPY %2:vgpr_32
S_ENDPGM 0, implicit %4
...
+
+---
+name: test_remat_v_pk_mov_b32
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_remat_v_pk_mov_b32
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[V_PK_MOV_B32_:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 8, 0, 8, 0, 0, 0, 0, 0, 0, implicit $exec
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[V_PK_MOV_B32_]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[V_PK_MOV_B32_]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr0
+ ; CHECK-NEXT: $exec = S_MOV_B64_term [[COPY2]]
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = V_PK_ADD_F32 8, [[COPY]], 8, [[COPY]], 11, 0, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = V_PK_ADD_F32 8, [[COPY1]], 8, [[COPY1]], 11, 0, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
+ ; CHECK-NEXT: S_NOP 0, implicit [[COPY1]]
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_PK_MOV_B32_]]
+ bb.0:
+ liveins: $sgpr0
+ %0:vreg_64_align2 = V_PK_MOV_B32 8, 0, 8, 0, 0, 0, 0, 0, 0, implicit $exec
+ %1:vreg_64_align2 = COPY %0:vreg_64_align2
+ %2:vreg_64_align2 = COPY %0:vreg_64_align2
+ %3:sreg_64 = COPY $sgpr0
+ $exec = S_MOV_B64_term %3:sreg_64
+ S_CBRANCH_EXECZ %bb.2, implicit $exec
+ S_BRANCH %bb.1
+
+ bb.1:
+ %1:vreg_64_align2 = V_PK_ADD_F32 8, %1, 8, %1, 11, 0, 0, 0, 0, implicit $mode, implicit $exec
+ %2:vreg_64_align2 = V_PK_ADD_F32 8, %2, 8, %2, 11, 0, 0, 0, 0, implicit $mode, implicit $exec
+
+ bb.2:
+ S_NOP 0, implicit %1
+ S_NOP 0, implicit %2
+ S_ENDPGM 0, implicit %0
+...
>From 2269c2354e9852beeeee340b0d5ec8dfea37af26 Mon Sep 17 00:00:00 2001
From: Shilei Tian <i at tianshilei.me>
Date: Tue, 18 Feb 2025 23:35:11 -0500
Subject: [PATCH 2/3] Move the test case out
---
.../AMDGPU/vgpr-remat-v_pk_mov_b32.mir | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/vgpr-remat-v_pk_mov_b32.mir
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-remat-v_pk_mov_b32.mir b/llvm/test/CodeGen/AMDGPU/vgpr-remat-v_pk_mov_b32.mir
new file mode 100644
index 0000000000000..c8d6bf386078f
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-remat-v_pk_mov_b32.mir
@@ -0,0 +1,49 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -run-pass=register-coalescer -o - %s | FileCheck %s
+
+---
+name: test_remat_v_pk_mov_b32
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_remat_v_pk_mov_b32
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[V_PK_MOV_B32_:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 8, 0, 8, 0, 0, 0, 0, 0, 0, implicit $exec
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[V_PK_MOV_B32_]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[V_PK_MOV_B32_]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr0
+ ; CHECK-NEXT: $exec = S_MOV_B64_term [[COPY2]]
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = V_PK_ADD_F32 8, [[COPY]], 8, [[COPY]], 11, 0, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = V_PK_ADD_F32 8, [[COPY1]], 8, [[COPY1]], 11, 0, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
+ ; CHECK-NEXT: S_NOP 0, implicit [[COPY1]]
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_PK_MOV_B32_]]
+ bb.0:
+ liveins: $sgpr0
+ %0:vreg_64_align2 = V_PK_MOV_B32 8, 0, 8, 0, 0, 0, 0, 0, 0, implicit $exec
+ %1:vreg_64_align2 = COPY %0:vreg_64_align2
+ %2:vreg_64_align2 = COPY %0:vreg_64_align2
+ %3:sreg_64 = COPY $sgpr0
+ $exec = S_MOV_B64_term %3:sreg_64
+ S_CBRANCH_EXECZ %bb.2, implicit $exec
+ S_BRANCH %bb.1
+
+ bb.1:
+ %1:vreg_64_align2 = V_PK_ADD_F32 8, %1, 8, %1, 11, 0, 0, 0, 0, implicit $mode, implicit $exec
+ %2:vreg_64_align2 = V_PK_ADD_F32 8, %2, 8, %2, 11, 0, 0, 0, 0, implicit $mode, implicit $exec
+
+ bb.2:
+ S_NOP 0, implicit %1
+ S_NOP 0, implicit %2
+ S_ENDPGM 0, implicit %0
+...
>From 3de655a14ced2d17fae1912500edce5ce2d2d78d Mon Sep 17 00:00:00 2001
From: Shilei Tian <i at tianshilei.me>
Date: Tue, 18 Feb 2025 23:39:22 -0500
Subject: [PATCH 3/3] remove redundant code
---
llvm/test/CodeGen/AMDGPU/vgpr-remat.mir | 47 -------------------------
1 file changed, 47 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-remat.mir b/llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
index 0d4f779b53976..08f5550f3b08a 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
@@ -46,50 +46,3 @@ body: |
%4.sub1:vreg_96 = COPY %2:vgpr_32
S_ENDPGM 0, implicit %4
...
-
----
-name: test_remat_v_pk_mov_b32
-tracksRegLiveness: true
-body: |
- ; CHECK-LABEL: name: test_remat_v_pk_mov_b32
- ; CHECK: bb.0:
- ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; CHECK-NEXT: liveins: $sgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[V_PK_MOV_B32_:%[0-9]+]]:vreg_64_align2 = V_PK_MOV_B32 8, 0, 8, 0, 0, 0, 0, 0, 0, implicit $exec
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY [[V_PK_MOV_B32_]]
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[V_PK_MOV_B32_]]
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr0
- ; CHECK-NEXT: $exec = S_MOV_B64_term [[COPY2]]
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: successors: %bb.2(0x80000000)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = V_PK_ADD_F32 8, [[COPY]], 8, [[COPY]], 11, 0, 0, 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = V_PK_ADD_F32 8, [[COPY1]], 8, [[COPY1]], 11, 0, 0, 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.2:
- ; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
- ; CHECK-NEXT: S_NOP 0, implicit [[COPY1]]
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_PK_MOV_B32_]]
- bb.0:
- liveins: $sgpr0
- %0:vreg_64_align2 = V_PK_MOV_B32 8, 0, 8, 0, 0, 0, 0, 0, 0, implicit $exec
- %1:vreg_64_align2 = COPY %0:vreg_64_align2
- %2:vreg_64_align2 = COPY %0:vreg_64_align2
- %3:sreg_64 = COPY $sgpr0
- $exec = S_MOV_B64_term %3:sreg_64
- S_CBRANCH_EXECZ %bb.2, implicit $exec
- S_BRANCH %bb.1
-
- bb.1:
- %1:vreg_64_align2 = V_PK_ADD_F32 8, %1, 8, %1, 11, 0, 0, 0, 0, implicit $mode, implicit $exec
- %2:vreg_64_align2 = V_PK_ADD_F32 8, %2, 8, %2, 11, 0, 0, 0, 0, implicit $mode, implicit $exec
-
- bb.2:
- S_NOP 0, implicit %1
- S_NOP 0, implicit %2
- S_ENDPGM 0, implicit %0
-...
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