[llvm] 27e6561 - [Sparc] Use MCRegister. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2025-02-18T19:59:59-08:00
New Revision: 27e6561d108e8a3c17432b14bb5e8675c22a787b

URL: https://github.com/llvm/llvm-project/commit/27e6561d108e8a3c17432b14bb5e8675c22a787b
DIFF: https://github.com/llvm/llvm-project/commit/27e6561d108e8a3c17432b14bb5e8675c22a787b.diff

LOG: [Sparc] Use MCRegister. NFC

Added: 
    

Modified: 
    llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
    llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
index 3e9fc31d7bfc2..62854ea896179 100644
--- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -525,7 +525,7 @@ class SparcOperand : public MCParsedAsmOperand {
   }
 
   static bool MorphToIntPairReg(SparcOperand &Op) {
-    unsigned Reg = Op.getReg();
+    MCRegister Reg = Op.getReg();
     assert(Op.Reg.Kind == rk_IntReg);
     unsigned regIdx = 32;
     if (Reg >= Sparc::G0 && Reg <= Sparc::G7)
@@ -544,7 +544,7 @@ class SparcOperand : public MCParsedAsmOperand {
   }
 
   static bool MorphToDoubleReg(SparcOperand &Op) {
-    unsigned Reg = Op.getReg();
+    MCRegister Reg = Op.getReg();
     assert(Op.Reg.Kind == rk_FloatReg);
     unsigned regIdx = Reg - Sparc::F0;
     if (regIdx % 2 || regIdx > 31)
@@ -555,7 +555,7 @@ class SparcOperand : public MCParsedAsmOperand {
   }
 
   static bool MorphToQuadReg(SparcOperand &Op) {
-    unsigned Reg = Op.getReg();
+    MCRegister Reg = Op.getReg();
     unsigned regIdx = 0;
     switch (Op.Reg.Kind) {
     default: llvm_unreachable("Unexpected register kind!");
@@ -578,7 +578,7 @@ class SparcOperand : public MCParsedAsmOperand {
   }
 
   static bool MorphToCoprocPairReg(SparcOperand &Op) {
-    unsigned Reg = Op.getReg();
+    MCRegister Reg = Op.getReg();
     assert(Op.Reg.Kind == rk_CoprocReg);
     unsigned regIdx = 32;
     if (Reg >= Sparc::C0 && Reg <= Sparc::C31)
@@ -592,7 +592,7 @@ class SparcOperand : public MCParsedAsmOperand {
 
   static std::unique_ptr<SparcOperand>
   MorphToMEMrr(unsigned Base, std::unique_ptr<SparcOperand> Op) {
-    unsigned offsetReg = Op->getReg();
+    MCRegister offsetReg = Op->getReg();
     Op->Kind = k_MemoryReg;
     Op->Mem.Base = Base;
     Op->Mem.OffsetReg = offsetReg;

diff  --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
index 37503f4bc2ae2..f2a61c95fefb5 100644
--- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
+++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
@@ -66,12 +66,12 @@ bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI,
       return false;
     if (!MI->getOperand(0).isReg())
       return false;
-    switch (MI->getOperand(0).getReg()) {
+    switch (MI->getOperand(0).getReg().id()) {
     default: return false;
     case SP::G0: // jmp $addr | ret | retl
       if (MI->getOperand(2).isImm() &&
           MI->getOperand(2).getImm() == 8) {
-        switch(MI->getOperand(1).getReg()) {
+        switch (MI->getOperand(1).getReg().id()) {
         default: break;
         case SP::I7: O << "\tret"; return true;
         case SP::O7: O << "\tretl"; return true;
@@ -115,7 +115,7 @@ void SparcInstPrinter::printOperand(const MCInst *MI, int opNum,
   const MCOperand &MO = MI->getOperand (opNum);
 
   if (MO.isReg()) {
-    unsigned Reg = MO.getReg();
+    MCRegister Reg = MO.getReg();
     if (isV9(STI))
       printRegName(O, Reg, SP::RegNamesStateReg);
     else