[llvm] [RISCV] Move VMV0 elimination past machine SSA opts (PR #126850)

[Philip Reames via llvm-commits]

https://github.com/preames commented:

I'm a bit hesitant about moving forward with this one given the noted weird register allocation behavior in the tests.  I see two paths forward:
1) Performance data which shows this is strongly net positive.
2) Investigating the regalloc cases, and fixing them in separate patches.  In particular, the spill/reload with no need to actually spill seems... weird.  

https://github.com/llvm/llvm-project/pull/126850