[llvm] [X86] matchUnaryShuffle - add support for matching 512-bit extension patterns. (PR #127643)

[Simon Pilgrim via llvm-commits]

================
@@ -13680,16 +13614,16 @@ define void @mask_replication_factor8_vf64(ptr %in.maskvec, ptr %in.vec, ptr %ou
 ; AVX512BW-NEXT:    vmovdqa64 {{.*#+}} zmm2 = [8,8,8,8,8,8,8,8,9,9,9,9,9,9,9,9,10,10,10,10,10,10,10,10,11,11,11,11,11,11,11,11,12,12,12,12,12,12,12,12,13,13,13,13,13,13,13,13,14,14,14,14,14,14,14,14,15,15,15,15,15,15,15,15]
 ; AVX512BW-NEXT:    vpshufb %zmm2, %zmm1, %zmm7
 ; AVX512BW-NEXT:    vmovdqa64 {{.*#+}} zmm3 = [0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,2,2,2,2,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,6,6,6,6,6,6,6,6,7,7,7,7,7,7,7,7]
-; AVX512BW-NEXT:    vpshufb %zmm3, %zmm1, %zmm12
+; AVX512BW-NEXT:    vpshufb %zmm3, %zmm1, %zmm10
 ; AVX512BW-NEXT:    vshufi64x2 {{.*#+}} zmm1 = zmm0[4,5,4,5,4,5,4,5]
 ; AVX512BW-NEXT:    vpshufb %zmm2, %zmm1, %zmm15
 ; AVX512BW-NEXT:    vpshufb %zmm3, %zmm1, %zmm16
 ; AVX512BW-NEXT:    vshufi64x2 {{.*#+}} zmm1 = zmm0[2,3,2,3,2,3,2,3]
-; AVX512BW-NEXT:    vpshufb %zmm2, %zmm1, %zmm10
+; AVX512BW-NEXT:    vpshufb %zmm2, %zmm1, %zmm11
 ; AVX512BW-NEXT:    vpshufb %zmm3, %zmm1, %zmm5
-; AVX512BW-NEXT:    vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,0,1,0,1,0,1]
-; AVX512BW-NEXT:    vpshufb %zmm2, %zmm0, %zmm1
-; AVX512BW-NEXT:    vpshufb %zmm3, %zmm0, %zmm0
+; AVX512BW-NEXT:    vshufi64x2 {{.*#+}} zmm1 = zmm0[0,1,0,1,0,1,0,1]
+; AVX512BW-NEXT:    vpshufb %zmm2, %zmm1, %zmm1
+; AVX512BW-NEXT:    vpmovsxbq %xmm0, %zmm0
----------------
RKSimon wrote:

Shuffle lowering doesn't handle SIGN_EXTEND patterns - we just have lowerShuffleAsZeroOrAnyExtend, so we rely on combining to deal with it at the moment.

https://github.com/llvm/llvm-project/pull/127643