[llvm] [RISCV] Move VMV0 elimination past machine SSA opts (PR #126850)

[Luke Lau via llvm-commits]

================
@@ -1515,40 +1515,36 @@ define <vscale x 16 x double> @vp_round_nxv16f64(<vscale x 16 x double> %va, <vs
 ; CHECK-NEXT:    vmv1r.v v0, v6
 ; CHECK-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
 ; CHECK-NEXT:    vfabs.v v24, v16, v0.t
+; CHECK-NEXT:    addi a2, sp, 16
+; CHECK-NEXT:    vs8r.v v24, (a2) # Unknown-size Folded Spill
+; CHECK-NEXT:    vl8r.v v24, (a2) # Unknown-size Folded Reload
----------------
lukel97 wrote:

I looked into this but couldn't really figure out what the register allocator was doing. It's spilling the %14 here

```
288B	  $v0 = COPY %6:vr
304B	  %18:vr = COPY %6:vr
320B	  early-clobber %18:vr = nofpexcept PseudoVMFLT_VFPR64_M8_MASK %18:vr(tied-def 0), %14:vrm8nov0, %17:fpr64, $v0, %13:gprnox0, 6
336B	  %39:gpr = SwapFRMImm 4, implicit-def $frm, implicit $frm
352B	  $v0 = COPY %18:vr
368B	  %20:vrm8nov0 = nofpexcept PseudoVFCVT_X_F_V_M8_MASK undef %20:vrm8nov0(tied-def 0), %1:vrm8nov0, $v0, 4, %13:gprnox0, 6, 3, implicit $frm
```

https://github.com/llvm/llvm-project/pull/126850