[llvm] RISCV: Implement isLoadFromStackSlot/isStoreToStackSlot for rvv (PR #120524)

[Luke Lau via llvm-commits]

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@@ -118,6 +118,15 @@ Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
   case RISCV::FLD:
     MemBytes = 8;
     break;
+  case RISCV::VL1RE8_V:
+  case RISCV::VL2RE8_V:
+  case RISCV::VL4RE8_V:
+  case RISCV::VL8RE8_V:
+    if (!MI.getOperand(1).isFI())
+      return Register();
+    FrameIndex = MI.getOperand(1).getIndex();
+    MemBytes = ~0u;
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lukel97 wrote:

Could also change the TTI signature to use TypeSize

https://github.com/llvm/llvm-project/pull/120524