[llvm] [RISCV] Add DAG combine to convert (iN reduce.add (zext (vXi1 A to vXiN)) into vcpop.m (PR #127497)

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git-clang-format --diff 8eba128b2dac8e405b663ef602f85469c3d6edb8 90d08bbf03990e87a8420d1c299eb1ff692a4228 --extensions cpp -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2a671075b1..28603fc736 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -18108,7 +18108,7 @@ static SDValue combineTruncToVnclip(SDNode *N, SelectionDAG &DAG,
 // legalization so we only handle the pre-type legalization pattern, but that
 // requires the fixed vector type to be legal.
 static SDValue combineToVCPOP(SDNode *N, SelectionDAG &DAG,
-                            const RISCVSubtarget &Subtarget) {
+                              const RISCVSubtarget &Subtarget) {
   unsigned Opc = N->getOpcode();
   assert((Opc == ISD::CTPOP || Opc == ISD::VECREDUCE_ADD) &&
          "Unexpected opcode");

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https://github.com/llvm/llvm-project/pull/127497