[llvm] Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (PR #127564)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff af1e2a374e3845454914348793341f4f931e805a f8ce0ccba940c41308353271d930a8628365a6c2 --extensions cpp -- llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
index dc312f4916..8d93350953 100644
--- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
@@ -59,17 +59,16 @@ static MCInst loadPPRImmediate(MCRegister Reg, unsigned RegBitWidth,
 static unsigned getLoadFPImmediateOpcode(unsigned RegBitWidth) {
   switch (RegBitWidth) {
   case 64:
-    return AArch64::FMOVDi; 
+    return AArch64::FMOVDi;
   case 128:
     return AArch64::MOVIv2d_ns;
   }
   llvm_unreachable("Invalid Value Width");
 }
 
-
 // Generates instruction to load an FP immediate value into a register.
 static MCInst loadFPImmediate(MCRegister Reg, unsigned RegBitWidth,
-                            const APInt &Value) {
+                              const APInt &Value) {
   if (Value.getBitWidth() > RegBitWidth)
     llvm_unreachable("Value must fit in the FP Register");
   return MCInstBuilder(getLoadFPImmediateOpcode(RegBitWidth))
@@ -95,16 +94,16 @@ private:
       return {loadImmediate(Reg, 64, Value)};
 
     if (AArch64::PPRRegClass.contains(Reg))
-      return {loadPPRImmediate(Reg, 16, Value)}; 
+      return {loadPPRImmediate(Reg, 16, Value)};
 
-    if (AArch64::FPR64RegClass.contains(Reg)) 
+    if (AArch64::FPR64RegClass.contains(Reg))
       return {loadFPImmediate(Reg, 64, Value)};
-    if (AArch64::FPR128RegClass.contains(Reg)) 
+    if (AArch64::FPR128RegClass.contains(Reg))
       return {loadFPImmediate(Reg, 128, Value)};
 
-    if (AArch64::ZPRRegClass.contains(Reg)) 
+    if (AArch64::ZPRRegClass.contains(Reg))
       return {loadZPRImmediate(Reg, 128, Value)};
-    
+
     errs() << "setRegTo is not implemented, results will be unreliable\n";
     return {};
   }

``````````

</details>


https://github.com/llvm/llvm-project/pull/127564