[llvm] AMDGPU: Allow only VGPR wide sources in fp6/4/8 conversions (PR #127464)

[Pravin Jagtap via llvm-commits]

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@@ -1818,6 +1818,18 @@ class getVOP3VRegSrcForVT<ValueType VT, bit IsTrue16 = 0, bit IsFake16 = 0> {
          1                 : RegisterOperand<VGPR_32>);
 }
 
+// VGPR only VOP3 src with 9 bit encoding
+class getVOP3VSrcReg9ForVT<ValueType VT> {
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pravinjagtap wrote:

The new method `getVOP3VSrcReg9ForVT` and the current `getVOP3VRegSrcForVT` are essentially different. I am not sure whether updating `getVOP3VRegSrcForVT` to use VRegSrc_* which additionally uses 9 bit encoding for decoding src:
```
// This is for operands with the enum(9), VSrc encoding restriction,
// but only allows VGPRs.
class SrcReg9<RegisterClass regClass, string width> : RegisterOperand<regClass> {
  let DecoderMethod = "decodeSrcReg9<AMDGPUDisassembler::" # width # ">";
}

def VRegSrc_32 : SrcReg9<VGPR_32, "OPW32">;
def VRegSrc_64 : SrcReg9<VReg_64, "OPW64">;
def VRegSrc_96 : SrcReg9<VReg_96, "OPW96">;
def VRegSrc_128: SrcReg9<VReg_128, "OPW128">;
def VRegSrc_192: SrcReg9<VReg_192, "OPW192">;
def VRegSrc_256: SrcReg9<VReg_256, "OPW256">;
def VRegSrc_512: SrcReg9<VReg_512, "OPW512">;
def VRegSrc_1024: SrcReg9<VReg_1024, "OPW1024">;
def VRegOrLdsSrc_32 : SrcReg9<VRegOrLds_32, "OPW32">;
```
is really required for all the uses of getVOP3VRegSrcForVT or not? but we need this for the `getVOP3VSrcReg9ForVT` which uses 9 bit encoding for gfx950.


https://github.com/llvm/llvm-project/pull/127464