[llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)

[Ricardo Jesus via llvm-commits]

================
@@ -237,8 +223,8 @@ define <vscale x 16 x i8> @ld_nxv16i8_offset(ptr %0) #0 {
 ;
 ; CHECK-128-LABEL: ld_nxv16i8_offset:
 ; CHECK-128:       // %bb.0:
-; CHECK-128-NEXT:    ptrue p0.b
-; CHECK-128-NEXT:    ld1b { z0.b }, p0/z, [x0, #1, mul vl]
+; CHECK-128-NEXT:    rdvl x8, #1
----------------
rj-jesus wrote:

The lowering for the `*_offset` versions could be improved, but if the equivalent ACLE code was compiled directly we wouldn't have `vscale` in the IR, and so would have the natural:
```
ldr	q0, [x0, #16]
```
and
```
str	q0, [x0, #16]
```

https://github.com/llvm/llvm-project/pull/127500