[llvm] [RISCV] Implement isHighLatencyDef() (PR #127476)

[Luke Lau via llvm-commits]

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@@ -3679,6 +3679,52 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
   return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
 }
 
+bool RISCVInstrInfo::isHighLatencyDef(int Opc) const {
+  switch (Opc) {
+  default:
+    return false;
+    // Integer div/rem.
+  case RISCV::DIV:
+  case RISCV::DIVW:
+  case RISCV::DIVU:
+  case RISCV::DIVUW:
+  case RISCV::REM:
+  case RISCV::REMW:
+  case RISCV::REMU:
+  case RISCV::REMUW:
+  // Floating-point div/rem/sqrt.
+  case RISCV::FDIV_H:
+  case RISCV::FDIV_S:
+  case RISCV::FDIV_D:
+  case RISCV::FDIV_H_INX:
+  case RISCV::FDIV_S_INX:
+  case RISCV::FDIV_D_INX:
+  case RISCV::FDIV_D_IN32X:
+  case RISCV::FSQRT_H:
+  case RISCV::FSQRT_S:
+  case RISCV::FSQRT_D:
+  case RISCV::FSQRT_H_INX:
+  case RISCV::FSQRT_S_INX:
+  case RISCV::FSQRT_D_INX:
+  case RISCV::FSQRT_D_IN32X:
+    // Integer div/rem.
+  case CASE_VFMA_OPCODE_VV(DIV):
+  case CASE_VFMA_OPCODE_VV(DIVU):
+  case CASE_VFMA_OPCODE_VV(REM):
+  case CASE_VFMA_OPCODE_VV(REMU):
+  // case CASE_VFMA_OPCODE_VX(DIV):
+  // case CASE_VFMA_OPCODE_VX(DIVU):
+  // case CASE_VFMA_OPCODE_VX(REM):
+  // case CASE_VFMA_OPCODE_VX(REMU):
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lukel97 wrote:

Are the .vx opcodes meant to be commented out? I assume they would be high latency too

https://github.com/llvm/llvm-project/pull/127476