[llvm] 02d4aac - [AMDGPU] Remove materializeImmediate (#127420)
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Sun Feb 16 22:47:18 PST 2025
Author: Kazu Hirata
Date: 2025-02-16T22:47:14-08:00
New Revision: 02d4aac55cdd1760ba9cda4aa512fe1a0240bf86
URL: https://github.com/llvm/llvm-project/commit/02d4aac55cdd1760ba9cda4aa512fe1a0240bf86
DIFF: https://github.com/llvm/llvm-project/commit/02d4aac55cdd1760ba9cda4aa512fe1a0240bf86.diff
LOG: [AMDGPU] Remove materializeImmediate (#127420)
The lase use was removed in:
commit cbf34a5f7701148d68951320a72f483849b22eaf
Author: Juan Manuel Martinez CaamaƱo <jmartinezcaamao at gmail.com>
Date: Fri Aug 23 14:06:17 2024 +0200
Added:
Modified:
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index baacb5d3d5455..8481c6333f479 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1171,62 +1171,6 @@ int SIInstrInfo::commuteOpcode(unsigned Opcode) const {
return Opcode;
}
-void SIInstrInfo::materializeImmediate(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- const DebugLoc &DL, Register DestReg,
- int64_t Value) const {
- MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
- const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
- if (RegClass == &AMDGPU::SReg_32RegClass ||
- RegClass == &AMDGPU::SGPR_32RegClass ||
- RegClass == &AMDGPU::SReg_32_XM0RegClass ||
- RegClass == &AMDGPU::SReg_32_XM0_XEXECRegClass) {
- BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
- .addImm(Value);
- return;
- }
-
- if (RegClass == &AMDGPU::SReg_64RegClass ||
- RegClass == &AMDGPU::SGPR_64RegClass ||
- RegClass == &AMDGPU::SReg_64_XEXECRegClass) {
- BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
- .addImm(Value);
- return;
- }
-
- if (RegClass == &AMDGPU::VGPR_32RegClass) {
- BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
- .addImm(Value);
- return;
- }
- if (RegClass->hasSuperClassEq(&AMDGPU::VReg_64RegClass)) {
- BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO), DestReg)
- .addImm(Value);
- return;
- }
-
- unsigned EltSize = 4;
- unsigned Opcode = AMDGPU::V_MOV_B32_e32;
- if (RI.isSGPRClass(RegClass)) {
- if (RI.getRegSizeInBits(*RegClass) > 32) {
- Opcode = AMDGPU::S_MOV_B64;
- EltSize = 8;
- } else {
- Opcode = AMDGPU::S_MOV_B32;
- EltSize = 4;
- }
- }
-
- ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RegClass, EltSize);
- for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
- int64_t IdxValue = Idx == 0 ? Value : 0;
-
- MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
- get(Opcode), RI.getSubReg(DestReg, SubIndices[Idx]));
- Builder.addImm(IdxValue);
- }
-}
-
const TargetRegisterClass *
SIInstrInfo::getPreferredSelectRegClass(unsigned Size) const {
return &AMDGPU::VGPR_32RegClass;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 6b0de138251ab..811e4fcbebf57 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -267,10 +267,6 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
- void materializeImmediate(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI, const DebugLoc &DL,
- Register DestReg, int64_t Value) const;
-
const TargetRegisterClass *getPreferredSelectRegClass(
unsigned Size) const;
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