[llvm] 9e8cd73 - [Mips] Use MCRegister. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 16 19:11:31 PST 2025
Author: Craig Topper
Date: 2025-02-16T19:10:49-08:00
New Revision: 9e8cd733c2643c92807a23b9b65099d9bb6bc560
URL: https://github.com/llvm/llvm-project/commit/9e8cd733c2643c92807a23b9b65099d9bb6bc560
DIFF: https://github.com/llvm/llvm-project/commit/9e8cd733c2643c92807a23b9b65099d9bb6bc560.diff
LOG: [Mips] Use MCRegister. NFC
Use id() to get rid of some implicit conversions.
Added:
Modified:
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h
llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
llvm/lib/Target/Mips/MipsAsmPrinter.cpp
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
llvm/lib/Target/Mips/MipsTargetStreamer.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index ff84a5e3d2b3b..d108564e128c0 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -224,12 +224,12 @@ class MipsAsmParser : public MCTargetAsmParser {
bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
- bool loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg,
+ bool loadImmediate(int64_t ImmValue, MCRegister DstReg, MCRegister SrcReg,
bool Is32BitImm, bool IsAddress, SMLoc IDLoc,
MCStreamer &Out, const MCSubtargetInfo *STI);
- bool loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
- unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc,
+ bool loadAndAddSymbolAddress(const MCExpr *SymExpr, MCRegister DstReg,
+ MCRegister SrcReg, bool Is32BitSym, SMLoc IDLoc,
MCStreamer &Out, const MCSubtargetInfo *STI);
bool emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym);
@@ -246,7 +246,7 @@ class MipsAsmParser : public MCTargetAsmParser {
bool expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, SMLoc IDLoc,
MCStreamer &Out, const MCSubtargetInfo *STI);
- bool expandLoadAddress(unsigned DstReg, unsigned BaseReg,
+ bool expandLoadAddress(MCRegister DstReg, MCRegister BaseReg,
const MCOperand &Offset, bool Is32BitAddress,
SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
@@ -428,12 +428,12 @@ class MipsAsmParser : public MCTargetAsmParser {
int matchMSA128CtrlRegisterName(StringRef Name);
- unsigned getReg(int RC, int RegNo);
+ MCRegister getReg(int RC, int RegNo);
/// Returns the internal register number for the current AT. Also checks if
/// the current AT is unavailable (set to $0) and gives an error if it is.
/// This should be used in pseudo-instruction expansions which need AT.
- unsigned getATReg(SMLoc Loc);
+ MCRegister getATReg(SMLoc Loc);
bool canUseATReg();
@@ -735,7 +735,7 @@ class MipsAsmParser : public MCTargetAsmParser {
void onEndOfFile() override;
/// Warn if RegIndex is the same as the current AT.
- void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);
+ void warnIfRegIndexIsAT(MCRegister RegIndex, SMLoc Loc);
void warnIfNoMacro(SMLoc Loc);
@@ -2123,7 +2123,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
// of the assembler. We ought to leave it to those later stages.
const MCSymbol *JalSym = getSingleMCSymbol(JalExpr);
- if (expandLoadAddress(Mips::T9, Mips::NoRegister, Inst.getOperand(0),
+ if (expandLoadAddress(Mips::T9, MCRegister(), Inst.getOperand(0),
!isGP64bit(), IDLoc, Out, STI))
return true;
@@ -2303,8 +2303,8 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
break;
case Mips::MOVEP_MM:
case Mips::MOVEP_MMR6: {
- unsigned R0 = Inst.getOperand(0).getReg();
- unsigned R1 = Inst.getOperand(1).getReg();
+ MCRegister R0 = Inst.getOperand(0).getReg();
+ MCRegister R1 = Inst.getOperand(1).getReg();
bool RegPair = ((R0 == Mips::A1 && R1 == Mips::A2) ||
(R0 == Mips::A1 && R1 == Mips::A3) ||
(R0 == Mips::A2 && R1 == Mips::A3) ||
@@ -2451,10 +2451,9 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
assert((Inst.getOperand(1).isImm() || Inst.getOperand(1).isExpr()) &&
"expected immediate operand kind");
- return expandLoadAddress(Inst.getOperand(0).getReg(), Mips::NoRegister,
- Inst.getOperand(1),
- Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc,
- Out, STI)
+ return expandLoadAddress(
+ Inst.getOperand(0).getReg(), MCRegister(), Inst.getOperand(1),
+ Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc, Out, STI)
? MER_Fail
: MER_Success;
case Mips::LoadAddrReg32:
@@ -2753,14 +2752,14 @@ template <unsigned N> static bool isShiftedUIntAtAnyPosition(uint64_t x) {
///
/// @param ImmValue The immediate to load.
/// @param DstReg The register that will hold the immediate.
-/// @param SrcReg A register to add to the immediate or Mips::NoRegister
+/// @param SrcReg A register to add to the immediate or MCRegister()
/// for a simple initialization.
/// @param Is32BitImm Is ImmValue 32-bit or 64-bit?
/// @param IsAddress True if the immediate represents an address. False if it
/// is an integer.
/// @param IDLoc Location of the immediate in the source file.
-bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
- unsigned SrcReg, bool Is32BitImm,
+bool MipsAsmParser::loadImmediate(int64_t ImmValue, MCRegister DstReg,
+ MCRegister SrcReg, bool Is32BitImm,
bool IsAddress, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
@@ -2782,19 +2781,19 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
}
}
- unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg();
+ MCRegister ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg();
unsigned AdduOp = !Is32BitImm ? Mips::DADDu : Mips::ADDu;
bool UseSrcReg = false;
- if (SrcReg != Mips::NoRegister)
+ if (SrcReg)
UseSrcReg = true;
- unsigned TmpReg = DstReg;
+ MCRegister TmpReg = DstReg;
if (UseSrcReg &&
getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) {
// At this point we need AT to perform the expansions and we exit if it is
// not available.
- unsigned ATReg = getATReg(IDLoc);
+ MCRegister ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
TmpReg = ATReg;
@@ -2817,7 +2816,7 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
}
if (isUInt<16>(ImmValue)) {
- unsigned TmpReg = DstReg;
+ MCRegister TmpReg = DstReg;
if (SrcReg == DstReg) {
TmpReg = getATReg(IDLoc);
if (!TmpReg)
@@ -2896,8 +2895,8 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
// The highest 32-bit's are equivalent to a 32-bit immediate load.
// Load bits 32-63 of ImmValue into bits 0-31 of the temporary register.
- if (loadImmediate(ImmValue >> 32, TmpReg, Mips::NoRegister, true, false,
- IDLoc, Out, STI))
+ if (loadImmediate(ImmValue >> 32, TmpReg, MCRegister(), true, false, IDLoc,
+ Out, STI))
return false;
// Shift and accumulate into the register. If a 16-bit chunk is zero, then
@@ -2933,14 +2932,14 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
const MCOperand &DstRegOp = Inst.getOperand(0);
assert(DstRegOp.isReg() && "expected register operand kind");
- if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
- Is32BitImm, false, IDLoc, Out, STI))
+ if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), MCRegister(), Is32BitImm,
+ false, IDLoc, Out, STI))
return true;
return false;
}
-bool MipsAsmParser::expandLoadAddress(unsigned DstReg, unsigned BaseReg,
+bool MipsAsmParser::expandLoadAddress(MCRegister DstReg, MCRegister BaseReg,
const MCOperand &Offset,
bool Is32BitAddress, SMLoc IDLoc,
MCStreamer &Out,
@@ -2972,13 +2971,13 @@ bool MipsAsmParser::expandLoadAddress(unsigned DstReg, unsigned BaseReg,
}
bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
- unsigned DstReg, unsigned SrcReg,
- bool Is32BitSym, SMLoc IDLoc,
- MCStreamer &Out,
+ MCRegister DstReg,
+ MCRegister SrcReg, bool Is32BitSym,
+ SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
- bool UseSrcReg = SrcReg != Mips::NoRegister && SrcReg != Mips::ZERO &&
- SrcReg != Mips::ZERO_64;
+ bool UseSrcReg =
+ SrcReg.isValid() && SrcReg != Mips::ZERO && SrcReg != Mips::ZERO_64;
warnIfNoMacro(IDLoc);
if (inPicMode()) {
@@ -3032,13 +3031,13 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
return false;
}
- unsigned TmpReg = DstReg;
+ MCRegister TmpReg = DstReg;
if (UseSrcReg &&
getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg,
SrcReg)) {
// If $rs is the same as $rd, we need to use AT.
// If it is not available we exit.
- unsigned ATReg = getATReg(IDLoc);
+ MCRegister ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
TmpReg = ATReg;
@@ -3171,7 +3170,7 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg);
if (canUseATReg() && UseSrcReg && RdRegIsRsReg) {
- unsigned ATReg = getATReg(IDLoc);
+ MCRegister ATReg = getATReg(IDLoc);
// If $rs is the same as $rd:
// (d)la $rd, sym($rd) => lui $at, %highest(sym)
@@ -3195,7 +3194,7 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
return false;
} else if (canUseATReg() && !RdRegIsRsReg && DstReg != getATReg(IDLoc)) {
- unsigned ATReg = getATReg(IDLoc);
+ MCRegister ATReg = getATReg(IDLoc);
// If the $rs is
diff erent from $rd or if $rs isn't specified and we
// have $at available:
@@ -3265,12 +3264,12 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
// (d)la $rd, sym/sym($rs) => lui $rd, %hi(sym)
// ori $rd, $rd, %lo(sym)
// (addu $rd, $rd, $rs)
- unsigned TmpReg = DstReg;
+ MCRegister TmpReg = DstReg;
if (UseSrcReg &&
getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) {
// If $rs is the same as $rd, we need to use AT.
// If it is not available we exit.
- unsigned ATReg = getATReg(IDLoc);
+ MCRegister ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
TmpReg = ATReg;
@@ -3292,10 +3291,10 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
// Each double-precision register DO-D15 overlaps with two of the single
// precision registers F0-F31. As an example, all of the following hold true:
// D0 + 1 == F1, F1 + 1 == D1, F1 + 1 == F2, depending on the context.
-static unsigned nextReg(unsigned Reg) {
+static MCRegister nextReg(MCRegister Reg) {
if (MipsMCRegisterClasses[Mips::FGR32RegClassID].contains(Reg))
return Reg == (unsigned)Mips::F31 ? (unsigned)Mips::F0 : Reg + 1;
- switch (Reg) {
+ switch (Reg.id()) {
default: llvm_unreachable("Unknown register in assembly macro expansion!");
case Mips::ZERO: return Mips::AT;
case Mips::AT: return Mips::V0;
@@ -3356,7 +3355,7 @@ static unsigned nextReg(unsigned Reg) {
// address to load a 64 bit value.
bool MipsAsmParser::emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc,
MCSymbol *Sym) {
- unsigned ATReg = getATReg(IDLoc);
+ MCRegister ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
@@ -3435,13 +3434,13 @@ bool MipsAsmParser::expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc,
assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() &&
"Invalid instruction operand.");
- unsigned FirstReg = Inst.getOperand(0).getReg();
+ MCRegister FirstReg = Inst.getOperand(0).getReg();
uint64_t ImmOp64 = Inst.getOperand(1).getImm();
uint32_t ImmOp32 = covertDoubleImmToSingleImm(convertIntToDoubleImm(ImmOp64));
- return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc,
- Out, STI);
+ return loadImmediate(ImmOp32, FirstReg, MCRegister(), true, false, IDLoc, Out,
+ STI);
}
bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc,
@@ -3452,14 +3451,14 @@ bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc,
assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() &&
"Invalid instruction operand.");
- unsigned FirstReg = Inst.getOperand(0).getReg();
+ MCRegister FirstReg = Inst.getOperand(0).getReg();
uint64_t ImmOp64 = Inst.getOperand(1).getImm();
ImmOp64 = convertIntToDoubleImm(ImmOp64);
uint32_t ImmOp32 = covertDoubleImmToSingleImm(ImmOp64);
- unsigned TmpReg = Mips::ZERO;
+ MCRegister TmpReg = Mips::ZERO;
if (ImmOp32 != 0) {
TmpReg = getATReg(IDLoc);
if (!TmpReg)
@@ -3467,7 +3466,7 @@ bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc,
}
if (Lo_32(ImmOp64) == 0) {
- if (TmpReg != Mips::ZERO && loadImmediate(ImmOp32, TmpReg, Mips::NoRegister,
+ if (TmpReg != Mips::ZERO && loadImmediate(ImmOp32, TmpReg, MCRegister(),
true, false, IDLoc, Out, STI))
return true;
TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI);
@@ -3506,23 +3505,23 @@ bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc,
assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() &&
"Invalid instruction operand.");
- unsigned FirstReg = Inst.getOperand(0).getReg();
+ MCRegister FirstReg = Inst.getOperand(0).getReg();
uint64_t ImmOp64 = Inst.getOperand(1).getImm();
ImmOp64 = convertIntToDoubleImm(ImmOp64);
if (Lo_32(ImmOp64) == 0) {
if (isGP64bit()) {
- if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false,
- IDLoc, Out, STI))
+ if (loadImmediate(ImmOp64, FirstReg, MCRegister(), false, false, IDLoc,
+ Out, STI))
return true;
} else {
- if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false,
+ if (loadImmediate(Hi_32(ImmOp64), FirstReg, MCRegister(), true, false,
IDLoc, Out, STI))
return true;
- if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, false,
- IDLoc, Out, STI))
+ if (loadImmediate(0, nextReg(FirstReg), MCRegister(), true, false, IDLoc,
+ Out, STI))
return true;
}
return false;
@@ -3544,7 +3543,7 @@ bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc,
getStreamer().emitIntValue(ImmOp64, 8);
getStreamer().switchSection(CS);
- unsigned TmpReg = getATReg(IDLoc);
+ MCRegister TmpReg = getATReg(IDLoc);
if (!TmpReg)
return true;
@@ -3571,12 +3570,12 @@ bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU,
assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() &&
"Invalid instruction operand.");
- unsigned FirstReg = Inst.getOperand(0).getReg();
+ MCRegister FirstReg = Inst.getOperand(0).getReg();
uint64_t ImmOp64 = Inst.getOperand(1).getImm();
ImmOp64 = convertIntToDoubleImm(ImmOp64);
- unsigned TmpReg = Mips::ZERO;
+ MCRegister TmpReg = Mips::ZERO;
if (ImmOp64 != 0) {
TmpReg = getATReg(IDLoc);
if (!TmpReg)
@@ -3586,17 +3585,16 @@ bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU,
if ((Lo_32(ImmOp64) == 0) &&
!((Hi_32(ImmOp64) & 0xffff0000) && (Hi_32(ImmOp64) & 0x0000ffff))) {
if (isGP64bit()) {
- if (TmpReg != Mips::ZERO &&
- loadImmediate(ImmOp64, TmpReg, Mips::NoRegister, false, false, IDLoc,
- Out, STI))
+ if (TmpReg != Mips::ZERO && loadImmediate(ImmOp64, TmpReg, MCRegister(),
+ false, false, IDLoc, Out, STI))
return true;
TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI);
return false;
}
if (TmpReg != Mips::ZERO &&
- loadImmediate(Hi_32(ImmOp64), TmpReg, Mips::NoRegister, true, false,
- IDLoc, Out, STI))
+ loadImmediate(Hi_32(ImmOp64), TmpReg, MCRegister(), true, false, IDLoc,
+ Out, STI))
return true;
if (hasMips32r2()) {
@@ -3729,12 +3727,12 @@ bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
} else {
warnIfNoMacro(IDLoc);
- unsigned ATReg = getATReg(IDLoc);
+ MCRegister ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
- if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, !isGP64bit(), true,
- IDLoc, Out, STI))
+ if (loadImmediate(ImmValue, ATReg, MCRegister(), !isGP64bit(), true, IDLoc,
+ Out, STI))
return true;
if (IsLikely) {
@@ -3761,9 +3759,9 @@ void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
MipsTargetStreamer &TOut = getTargetStreamer();
unsigned OpCode = Inst.getOpcode();
- unsigned DstReg = DstRegOp.getReg();
- unsigned BaseReg = BaseRegOp.getReg();
- unsigned TmpReg = DstReg;
+ MCRegister DstReg = DstRegOp.getReg();
+ MCRegister BaseReg = BaseRegOp.getReg();
+ MCRegister TmpReg = DstReg;
const MCInstrDesc &Desc = MII.get(OpCode);
int16_t DstRegClass = Desc.operands()[StartOp].RegClass;
@@ -3800,8 +3798,8 @@ void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
if (IsLargeOffset) {
bool Is32BitImm = isInt<32>(OffsetOp.getImm());
- if (loadImmediate(HiOffset, TmpReg, Mips::NoRegister, Is32BitImm, true,
- IDLoc, Out, STI))
+ if (loadImmediate(HiOffset, TmpReg, MCRegister(), Is32BitImm, true, IDLoc,
+ Out, STI))
return;
}
@@ -3888,9 +3886,9 @@ void MipsAsmParser::expandMem9Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
MipsTargetStreamer &TOut = getTargetStreamer();
unsigned OpCode = Inst.getOpcode();
- unsigned DstReg = DstRegOp.getReg();
- unsigned BaseReg = BaseRegOp.getReg();
- unsigned TmpReg = DstReg;
+ MCRegister DstReg = DstRegOp.getReg();
+ MCRegister BaseReg = BaseRegOp.getReg();
+ MCRegister TmpReg = DstReg;
const MCInstrDesc &Desc = MII.get(OpCode);
int16_t DstRegClass = Desc.operands()[StartOp].RegClass;
@@ -3967,14 +3965,14 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
MipsTargetStreamer &TOut = getTargetStreamer();
bool EmittedNoMacroWarning = false;
unsigned PseudoOpcode = Inst.getOpcode();
- unsigned SrcReg = Inst.getOperand(0).getReg();
+ MCRegister SrcReg = Inst.getOperand(0).getReg();
const MCOperand &TrgOp = Inst.getOperand(1);
const MCExpr *OffsetExpr = Inst.getOperand(2).getExpr();
unsigned ZeroSrcOpcode, ZeroTrgOpcode;
bool ReverseOrderSLT, IsUnsigned, IsLikely, AcceptsEquality;
- unsigned TrgReg;
+ MCRegister TrgReg;
if (TrgOp.isReg())
TrgReg = TrgOp.getReg();
else if (TrgOp.isImm()) {
@@ -4038,8 +4036,8 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
break;
}
- if (loadImmediate(TrgOp.getImm(), TrgReg, Mips::NoRegister, !isGP64bit(),
- false, IDLoc, Out, STI))
+ if (loadImmediate(TrgOp.getImm(), TrgReg, MCRegister(), !isGP64bit(), false,
+ IDLoc, Out, STI))
return true;
}
@@ -4191,7 +4189,7 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
// If neither the SrcReg nor the TrgReg are $0, we need AT to perform the
// expansions. If it is not available, we return.
- unsigned ATRegNum = getATReg(IDLoc);
+ MCRegister ATRegNum = getATReg(IDLoc);
if (!ATRegNum)
return true;
@@ -4241,13 +4239,13 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCOperand &RdRegOp = Inst.getOperand(0);
assert(RdRegOp.isReg() && "expected register operand kind");
- unsigned RdReg = RdRegOp.getReg();
+ MCRegister RdReg = RdRegOp.getReg();
const MCOperand &RsRegOp = Inst.getOperand(1);
assert(RsRegOp.isReg() && "expected register operand kind");
- unsigned RsReg = RsRegOp.getReg();
+ MCRegister RsReg = RsRegOp.getReg();
- unsigned RtReg;
+ MCRegister RtReg;
int64_t ImmValue;
const MCOperand &RtOp = Inst.getOperand(2);
@@ -4286,7 +4284,7 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
Opcode == Mips::DURemMacro || Opcode == Mips::DURemIMacro;
if (RtOp.isImm()) {
- unsigned ATReg = getATReg(IDLoc);
+ MCRegister ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
@@ -4308,7 +4306,7 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI);
return false;
} else {
- if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue),
+ if (loadImmediate(ImmValue, ATReg, MCRegister(), isInt<32>(ImmValue),
false, Inst.getLoc(), Out, STI))
return true;
TOut.emitRR(DivOp, RsReg, ATReg, IDLoc, STI);
@@ -4365,7 +4363,7 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
return false;
}
- unsigned ATReg = getATReg(IDLoc);
+ MCRegister ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
@@ -4412,12 +4410,12 @@ bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU,
assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() &&
Inst.getOperand(2).isReg() && "Invalid instruction operand.");
- unsigned FirstReg = Inst.getOperand(0).getReg();
- unsigned SecondReg = Inst.getOperand(1).getReg();
- unsigned ThirdReg = Inst.getOperand(2).getReg();
+ MCRegister FirstReg = Inst.getOperand(0).getReg();
+ MCRegister SecondReg = Inst.getOperand(1).getReg();
+ MCRegister ThirdReg = Inst.getOperand(2).getReg();
if (hasMips1() && !hasMips2()) {
- unsigned ATReg = getATReg(IDLoc);
+ MCRegister ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
@@ -4456,14 +4454,14 @@ bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
assert(OffsetImmOp.isImm() && "expected immediate operand kind");
MipsTargetStreamer &TOut = getTargetStreamer();
- unsigned DstReg = DstRegOp.getReg();
- unsigned SrcReg = SrcRegOp.getReg();
+ MCRegister DstReg = DstRegOp.getReg();
+ MCRegister SrcReg = SrcRegOp.getReg();
int64_t OffsetValue = OffsetImmOp.getImm();
// NOTE: We always need AT for ULHU, as it is always used as the source
// register for one of the LBu's.
warnIfNoMacro(IDLoc);
- unsigned ATReg = getATReg(IDLoc);
+ MCRegister ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
@@ -4479,11 +4477,11 @@ bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
if (isLittle())
std::swap(FirstOffset, SecondOffset);
- unsigned FirstLbuDstReg = IsLargeOffset ? DstReg : ATReg;
- unsigned SecondLbuDstReg = IsLargeOffset ? ATReg : DstReg;
+ MCRegister FirstLbuDstReg = IsLargeOffset ? DstReg : ATReg;
+ MCRegister SecondLbuDstReg = IsLargeOffset ? ATReg : DstReg;
- unsigned LbuSrcReg = IsLargeOffset ? ATReg : SrcReg;
- unsigned SllReg = IsLargeOffset ? DstReg : ATReg;
+ MCRegister LbuSrcReg = IsLargeOffset ? ATReg : SrcReg;
+ MCRegister SllReg = IsLargeOffset ? DstReg : ATReg;
TOut.emitRRI(Signed ? Mips::LB : Mips::LBu, FirstLbuDstReg, LbuSrcReg,
FirstOffset, IDLoc, STI);
@@ -4508,12 +4506,12 @@ bool MipsAsmParser::expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
assert(OffsetImmOp.isImm() && "expected immediate operand kind");
MipsTargetStreamer &TOut = getTargetStreamer();
- unsigned DstReg = DstRegOp.getReg();
- unsigned SrcReg = SrcRegOp.getReg();
+ MCRegister DstReg = DstRegOp.getReg();
+ MCRegister SrcReg = SrcRegOp.getReg();
int64_t OffsetValue = OffsetImmOp.getImm();
warnIfNoMacro(IDLoc);
- unsigned ATReg = getATReg(IDLoc);
+ MCRegister ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
@@ -4559,8 +4557,8 @@ bool MipsAsmParser::expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
assert(OffsetImmOp.isImm() && "expected immediate operand kind");
MipsTargetStreamer &TOut = getTargetStreamer();
- unsigned DstReg = DstRegOp.getReg();
- unsigned SrcReg = SrcRegOp.getReg();
+ MCRegister DstReg = DstRegOp.getReg();
+ MCRegister SrcReg = SrcRegOp.getReg();
int64_t OffsetValue = OffsetImmOp.getImm();
// Compute left/right load/store offsets.
@@ -4572,7 +4570,7 @@ bool MipsAsmParser::expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
bool IsLoadInst = (Inst.getOpcode() == Mips::Ulw);
bool DoMove = IsLoadInst && (SrcReg == DstReg) && !IsLargeOffset;
- unsigned TmpReg = SrcReg;
+ MCRegister TmpReg = SrcReg;
if (IsLargeOffset || DoMove) {
warnIfNoMacro(IDLoc);
TmpReg = getATReg(IDLoc);
@@ -4609,9 +4607,9 @@ bool MipsAsmParser::expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
Inst.getOperand(1).isReg() &&
Inst.getOperand(2).isReg() && "Invalid instruction operand.");
- unsigned DstReg = Inst.getOperand(0).getReg();
- unsigned SrcReg = Inst.getOperand(1).getReg();
- unsigned OpReg = Inst.getOperand(2).getReg();
+ MCRegister DstReg = Inst.getOperand(0).getReg();
+ MCRegister SrcReg = Inst.getOperand(1).getReg();
+ MCRegister OpReg = Inst.getOperand(2).getReg();
unsigned OpCode;
warnIfNoMacro(IDLoc);
@@ -4643,8 +4641,8 @@ bool MipsAsmParser::expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
Inst.getOperand(1).isReg() &&
Inst.getOperand(2).isImm() && "Invalid instruction operand.");
- unsigned DstReg = Inst.getOperand(0).getReg();
- unsigned SrcReg = Inst.getOperand(1).getReg();
+ MCRegister DstReg = Inst.getOperand(0).getReg();
+ MCRegister SrcReg = Inst.getOperand(1).getReg();
int64_t ImmValue = Inst.getOperand(2).getImm();
unsigned OpRegCode, OpImmCode;
@@ -4671,15 +4669,15 @@ bool MipsAsmParser::expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
TOut.emitRRI(OpImmCode, DstReg, SrcReg, ImmValue, IDLoc, STI);
TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
} else {
- unsigned ImmReg = DstReg;
+ MCRegister ImmReg = DstReg;
if (DstReg == SrcReg) {
- unsigned ATReg = getATReg(Inst.getLoc());
+ MCRegister ATReg = getATReg(Inst.getLoc());
if (!ATReg)
return true;
ImmReg = ATReg;
}
- if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
+ if (loadImmediate(ImmValue, ImmReg, MCRegister(), isInt<32>(ImmValue),
false, IDLoc, Out, STI))
return true;
@@ -4699,9 +4697,9 @@ bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
Inst.getOperand(1).isReg() &&
Inst.getOperand(2).isImm() && "Invalid instruction operand.");
- unsigned DstReg = Inst.getOperand(0).getReg();
- unsigned SrcReg = Inst.getOperand(1).getReg();
- unsigned ImmReg = DstReg;
+ MCRegister DstReg = Inst.getOperand(0).getReg();
+ MCRegister SrcReg = Inst.getOperand(1).getReg();
+ MCRegister ImmReg = DstReg;
int64_t ImmValue = Inst.getOperand(2).getImm();
unsigned OpCode;
@@ -4721,14 +4719,14 @@ bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
}
if (DstReg == SrcReg) {
- unsigned ATReg = getATReg(Inst.getLoc());
+ MCRegister ATReg = getATReg(Inst.getLoc());
if (!ATReg)
return true;
ImmReg = ATReg;
}
- if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
- false, IDLoc, Out, STI))
+ if (loadImmediate(ImmValue, ImmReg, MCRegister(), isInt<32>(ImmValue), false,
+ IDLoc, Out, STI))
return true;
// $SrcReg > $ImmReg is equal to $ImmReg < $SrcReg
@@ -4746,9 +4744,9 @@ bool MipsAsmParser::expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
Inst.getOperand(1).isReg() &&
Inst.getOperand(2).isReg() && "Invalid instruction operand.");
- unsigned DstReg = Inst.getOperand(0).getReg();
- unsigned SrcReg = Inst.getOperand(1).getReg();
- unsigned OpReg = Inst.getOperand(2).getReg();
+ MCRegister DstReg = Inst.getOperand(0).getReg();
+ MCRegister SrcReg = Inst.getOperand(1).getReg();
+ MCRegister OpReg = Inst.getOperand(2).getReg();
unsigned OpCode;
warnIfNoMacro(IDLoc);
@@ -4780,8 +4778,8 @@ bool MipsAsmParser::expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
Inst.getOperand(1).isReg() &&
Inst.getOperand(2).isImm() && "Invalid instruction operand.");
- unsigned DstReg = Inst.getOperand(0).getReg();
- unsigned SrcReg = Inst.getOperand(1).getReg();
+ MCRegister DstReg = Inst.getOperand(0).getReg();
+ MCRegister SrcReg = Inst.getOperand(1).getReg();
int64_t ImmValue = Inst.getOperand(2).getImm();
unsigned OpRegCode;
@@ -4801,16 +4799,16 @@ bool MipsAsmParser::expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
}
// $SrcReg <= Imm is equal to (not (Imm < $SrcReg))
- unsigned ImmReg = DstReg;
+ MCRegister ImmReg = DstReg;
if (DstReg == SrcReg) {
- unsigned ATReg = getATReg(Inst.getLoc());
+ MCRegister ATReg = getATReg(Inst.getLoc());
if (!ATReg)
return true;
ImmReg = ATReg;
}
- if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
- false, IDLoc, Out, STI))
+ if (loadImmediate(ImmValue, ImmReg, MCRegister(), isInt<32>(ImmValue), false,
+ IDLoc, Out, STI))
return true;
TOut.emitRRR(OpRegCode, DstReg, ImmReg, SrcReg, IDLoc, STI);
@@ -4829,10 +4827,10 @@ bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc,
Inst.getOperand(1).isReg() &&
Inst.getOperand(2).isImm() && "Invalid instruction operand.");
- unsigned ATReg = Mips::NoRegister;
- unsigned FinalDstReg = Mips::NoRegister;
- unsigned DstReg = Inst.getOperand(0).getReg();
- unsigned SrcReg = Inst.getOperand(1).getReg();
+ MCRegister ATReg;
+ MCRegister FinalDstReg;
+ MCRegister DstReg = Inst.getOperand(0).getReg();
+ MCRegister SrcReg = Inst.getOperand(1).getReg();
int64_t ImmValue = Inst.getOperand(2).getImm();
bool Is32Bit = isInt<32>(ImmValue) || (!isGP64bit() && isUInt<32>(ImmValue));
@@ -4847,7 +4845,7 @@ bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc,
DstReg = ATReg;
}
- if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false,
+ if (!loadImmediate(ImmValue, DstReg, MCRegister(), Is32Bit, false,
Inst.getLoc(), Out, STI)) {
switch (FinalOpcode) {
default:
@@ -4917,7 +4915,7 @@ bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc,
break;
}
- if (FinalDstReg == Mips::NoRegister)
+ if (!FinalDstReg)
TOut.emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, STI);
else
TOut.emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, STI);
@@ -4929,11 +4927,11 @@ bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc,
bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
- unsigned ATReg = Mips::NoRegister;
- unsigned DReg = Inst.getOperand(0).getReg();
- unsigned SReg = Inst.getOperand(1).getReg();
- unsigned TReg = Inst.getOperand(2).getReg();
- unsigned TmpReg = DReg;
+ MCRegister ATReg;
+ MCRegister DReg = Inst.getOperand(0).getReg();
+ MCRegister SReg = Inst.getOperand(1).getReg();
+ MCRegister TReg = Inst.getOperand(2).getReg();
+ MCRegister TmpReg = DReg;
unsigned FirstShift = Mips::NOP;
unsigned SecondShift = Mips::NOP;
@@ -4992,9 +4990,9 @@ bool MipsAsmParser::expandRotationImm(MCInst &Inst, SMLoc IDLoc,
MCStreamer &Out,
const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
- unsigned ATReg = Mips::NoRegister;
- unsigned DReg = Inst.getOperand(0).getReg();
- unsigned SReg = Inst.getOperand(1).getReg();
+ MCRegister ATReg;
+ MCRegister DReg = Inst.getOperand(0).getReg();
+ MCRegister SReg = Inst.getOperand(1).getReg();
int64_t ImmValue = Inst.getOperand(2).getImm();
unsigned FirstShift = Mips::NOP;
@@ -5054,11 +5052,11 @@ bool MipsAsmParser::expandRotationImm(MCInst &Inst, SMLoc IDLoc,
bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
- unsigned ATReg = Mips::NoRegister;
- unsigned DReg = Inst.getOperand(0).getReg();
- unsigned SReg = Inst.getOperand(1).getReg();
- unsigned TReg = Inst.getOperand(2).getReg();
- unsigned TmpReg = DReg;
+ MCRegister ATReg;
+ MCRegister DReg = Inst.getOperand(0).getReg();
+ MCRegister SReg = Inst.getOperand(1).getReg();
+ MCRegister TReg = Inst.getOperand(2).getReg();
+ MCRegister TmpReg = DReg;
unsigned FirstShift = Mips::NOP;
unsigned SecondShift = Mips::NOP;
@@ -5117,9 +5115,9 @@ bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc,
MCStreamer &Out,
const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
- unsigned ATReg = Mips::NoRegister;
- unsigned DReg = Inst.getOperand(0).getReg();
- unsigned SReg = Inst.getOperand(1).getReg();
+ MCRegister ATReg;
+ MCRegister DReg = Inst.getOperand(0).getReg();
+ MCRegister SReg = Inst.getOperand(1).getReg();
int64_t ImmValue = Inst.getOperand(2).getImm() % 64;
unsigned FirstShift = Mips::NOP;
@@ -5211,8 +5209,8 @@ bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc,
bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
- unsigned FirstRegOp = Inst.getOperand(0).getReg();
- unsigned SecondRegOp = Inst.getOperand(1).getReg();
+ MCRegister FirstRegOp = Inst.getOperand(0).getReg();
+ MCRegister SecondRegOp = Inst.getOperand(1).getReg();
TOut.emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, STI);
if (FirstRegOp != SecondRegOp)
@@ -5227,17 +5225,16 @@ bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
- unsigned ATReg = Mips::NoRegister;
- unsigned DstReg = Inst.getOperand(0).getReg();
- unsigned SrcReg = Inst.getOperand(1).getReg();
+ MCRegister ATReg;
+ MCRegister DstReg = Inst.getOperand(0).getReg();
+ MCRegister SrcReg = Inst.getOperand(1).getReg();
int32_t ImmValue = Inst.getOperand(2).getImm();
ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
- loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, IDLoc, Out,
- STI);
+ loadImmediate(ImmValue, ATReg, MCRegister(), true, false, IDLoc, Out, STI);
TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT,
SrcReg, ATReg, IDLoc, STI);
@@ -5250,10 +5247,10 @@ bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
- unsigned ATReg = Mips::NoRegister;
- unsigned DstReg = Inst.getOperand(0).getReg();
- unsigned SrcReg = Inst.getOperand(1).getReg();
- unsigned TmpReg = Inst.getOperand(2).getReg();
+ MCRegister ATReg;
+ MCRegister DstReg = Inst.getOperand(0).getReg();
+ MCRegister SrcReg = Inst.getOperand(1).getReg();
+ MCRegister TmpReg = Inst.getOperand(2).getReg();
ATReg = getATReg(Inst.getLoc());
if (!ATReg)
@@ -5292,10 +5289,10 @@ bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
- unsigned ATReg = Mips::NoRegister;
- unsigned DstReg = Inst.getOperand(0).getReg();
- unsigned SrcReg = Inst.getOperand(1).getReg();
- unsigned TmpReg = Inst.getOperand(2).getReg();
+ MCRegister ATReg;
+ MCRegister DstReg = Inst.getOperand(0).getReg();
+ MCRegister SrcReg = Inst.getOperand(1).getReg();
+ MCRegister TmpReg = Inst.getOperand(2).getReg();
ATReg = getATReg(IDLoc);
if (!ATReg)
@@ -5328,9 +5325,9 @@ bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
bool MipsAsmParser::expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
- unsigned DstReg = Inst.getOperand(0).getReg();
- unsigned SrcReg = Inst.getOperand(1).getReg();
- unsigned TmpReg = Inst.getOperand(2).getReg();
+ MCRegister DstReg = Inst.getOperand(0).getReg();
+ MCRegister SrcReg = Inst.getOperand(1).getReg();
+ MCRegister TmpReg = Inst.getOperand(2).getReg();
TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI);
TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
@@ -5354,9 +5351,9 @@ bool MipsAsmParser::expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc,
MipsTargetStreamer &TOut = getTargetStreamer();
unsigned Opcode = IsLoad ? Mips::LW : Mips::SW;
- unsigned FirstReg = Inst.getOperand(0).getReg();
- unsigned SecondReg = nextReg(FirstReg);
- unsigned BaseReg = Inst.getOperand(1).getReg();
+ MCRegister FirstReg = Inst.getOperand(0).getReg();
+ MCRegister SecondReg = nextReg(FirstReg);
+ MCRegister BaseReg = Inst.getOperand(1).getReg();
if (!SecondReg)
return true;
@@ -5401,9 +5398,9 @@ bool MipsAsmParser::expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc,
MipsTargetStreamer &TOut = getTargetStreamer();
unsigned Opcode = Mips::SWC1;
- unsigned FirstReg = Inst.getOperand(0).getReg();
- unsigned SecondReg = nextReg(FirstReg);
- unsigned BaseReg = Inst.getOperand(1).getReg();
+ MCRegister FirstReg = Inst.getOperand(0).getReg();
+ MCRegister SecondReg = nextReg(FirstReg);
+ MCRegister BaseReg = Inst.getOperand(1).getReg();
if (!SecondReg)
return true;
@@ -5437,9 +5434,9 @@ bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
Inst.getOperand(1).isReg() &&
Inst.getOperand(2).isReg() && "Invalid instruction operand.");
- unsigned DstReg = Inst.getOperand(0).getReg();
- unsigned SrcReg = Inst.getOperand(1).getReg();
- unsigned OpReg = Inst.getOperand(2).getReg();
+ MCRegister DstReg = Inst.getOperand(0).getReg();
+ MCRegister SrcReg = Inst.getOperand(1).getReg();
+ MCRegister OpReg = Inst.getOperand(2).getReg();
warnIfNoMacro(IDLoc);
@@ -5449,7 +5446,7 @@ bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
return false;
}
- unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg;
+ MCRegister Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg;
TOut.emitRRI(Mips::SLTiu, DstReg, Reg, 1, IDLoc, STI);
return false;
}
@@ -5463,8 +5460,8 @@ bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
Inst.getOperand(1).isReg() &&
Inst.getOperand(2).isImm() && "Invalid instruction operand.");
- unsigned DstReg = Inst.getOperand(0).getReg();
- unsigned SrcReg = Inst.getOperand(1).getReg();
+ MCRegister DstReg = Inst.getOperand(0).getReg();
+ MCRegister SrcReg = Inst.getOperand(1).getReg();
int64_t Imm = Inst.getOperand(2).getImm();
warnIfNoMacro(IDLoc);
@@ -5490,12 +5487,12 @@ bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
}
if (!isUInt<16>(Imm)) {
- unsigned ATReg = getATReg(IDLoc);
+ MCRegister ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
- if (loadImmediate(Imm, ATReg, Mips::NoRegister, true, isGP64bit(), IDLoc,
- Out, STI))
+ if (loadImmediate(Imm, ATReg, MCRegister(), true, isGP64bit(), IDLoc, Out,
+ STI))
return true;
TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI);
@@ -5518,9 +5515,9 @@ bool MipsAsmParser::expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
Inst.getOperand(1).isReg() &&
Inst.getOperand(2).isReg() && "Invalid instruction operand.");
- unsigned DstReg = Inst.getOperand(0).getReg();
- unsigned SrcReg = Inst.getOperand(1).getReg();
- unsigned OpReg = Inst.getOperand(2).getReg();
+ MCRegister DstReg = Inst.getOperand(0).getReg();
+ MCRegister SrcReg = Inst.getOperand(1).getReg();
+ MCRegister OpReg = Inst.getOperand(2).getReg();
warnIfNoMacro(IDLoc);
@@ -5530,7 +5527,7 @@ bool MipsAsmParser::expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
return false;
}
- unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg;
+ MCRegister Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg;
TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, Reg, IDLoc, STI);
return false;
}
@@ -5544,8 +5541,8 @@ bool MipsAsmParser::expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
Inst.getOperand(1).isReg() &&
Inst.getOperand(2).isImm() && "Invalid instruction operand.");
- unsigned DstReg = Inst.getOperand(0).getReg();
- unsigned SrcReg = Inst.getOperand(1).getReg();
+ MCRegister DstReg = Inst.getOperand(0).getReg();
+ MCRegister SrcReg = Inst.getOperand(1).getReg();
int64_t ImmValue = Inst.getOperand(2).getImm();
warnIfNoMacro(IDLoc);
@@ -5557,8 +5554,7 @@ bool MipsAsmParser::expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
if (SrcReg == Mips::ZERO) {
Warning(IDLoc, "comparison is always true");
- if (loadImmediate(1, DstReg, Mips::NoRegister, true, false, IDLoc, Out,
- STI))
+ if (loadImmediate(1, DstReg, MCRegister(), true, false, IDLoc, Out, STI))
return true;
return false;
}
@@ -5577,12 +5573,12 @@ bool MipsAsmParser::expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
return false;
}
- unsigned ATReg = getATReg(IDLoc);
+ MCRegister ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
- if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue),
- false, IDLoc, Out, STI))
+ if (loadImmediate(ImmValue, ATReg, MCRegister(), isInt<32>(ImmValue), false,
+ IDLoc, Out, STI))
return true;
TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI);
@@ -5597,7 +5593,7 @@ static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {
switch (Inst.getOpcode()) {
case Mips::MFTLO:
case Mips::MTTLO:
- switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
+ switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg().id()) {
case Mips::AC0:
return Mips::ZERO;
case Mips::AC1:
@@ -5611,7 +5607,7 @@ static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {
}
case Mips::MFTHI:
case Mips::MTTHI:
- switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
+ switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg().id()) {
case Mips::AC0:
return Mips::AT;
case Mips::AC1:
@@ -5625,7 +5621,7 @@ static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {
}
case Mips::MFTACX:
case Mips::MTTACX:
- switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
+ switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg().id()) {
case Mips::AC0:
return Mips::V0;
case Mips::AC1:
@@ -5648,7 +5644,7 @@ static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {
// Map the floating point register operand to the corresponding register
// operand.
static unsigned getRegisterForMxtrFP(MCInst &Inst, bool IsMFTC1) {
- switch (Inst.getOperand(IsMFTC1 ? 1 : 0).getReg()) {
+ switch (Inst.getOperand(IsMFTC1 ? 1 : 0).getReg().id()) {
case Mips::F0: return Mips::ZERO;
case Mips::F1: return Mips::AT;
case Mips::F2: return Mips::V0;
@@ -5687,7 +5683,7 @@ static unsigned getRegisterForMxtrFP(MCInst &Inst, bool IsMFTC1) {
// Map the coprocessor operand the corresponding gpr register operand.
static unsigned getRegisterForMxtrC0(MCInst &Inst, bool IsMFTC0) {
- switch (Inst.getOperand(IsMFTC0 ? 1 : 0).getReg()) {
+ switch (Inst.getOperand(IsMFTC0 ? 1 : 0).getReg().id()) {
case Mips::COP00: return Mips::ZERO;
case Mips::COP01: return Mips::AT;
case Mips::COP02: return Mips::V0;
@@ -5729,7 +5725,7 @@ static unsigned getRegisterForMxtrC0(MCInst &Inst, bool IsMFTC0) {
bool MipsAsmParser::expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
- unsigned rd = 0;
+ MCRegister rd;
unsigned u = 1;
unsigned sel = 0;
unsigned h = 0;
@@ -5806,8 +5802,8 @@ bool MipsAsmParser::expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
MipsTargetStreamer &TOut = getTargetStreamer();
unsigned Opcode = Inst.getOpcode() == Mips::SaaAddr ? Mips::SAA : Mips::SAAD;
- unsigned RtReg = Inst.getOperand(0).getReg();
- unsigned BaseReg = Inst.getOperand(1).getReg();
+ MCRegister RtReg = Inst.getOperand(0).getReg();
+ MCRegister BaseReg = Inst.getOperand(1).getReg();
const MCOperand &BaseOp = Inst.getOperand(2);
if (BaseOp.isImm()) {
@@ -5818,7 +5814,7 @@ bool MipsAsmParser::expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
}
}
- unsigned ATReg = getATReg(IDLoc);
+ MCRegister ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
@@ -6197,9 +6193,9 @@ bool MipsAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
llvm_unreachable("Implement any new match types added!");
}
-void MipsAsmParser::warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc) {
- if (RegIndex != 0 && AssemblerOptions.back()->getATRegIndex() == RegIndex)
- Warning(Loc, "used $at (currently $" + Twine(RegIndex) +
+void MipsAsmParser::warnIfRegIndexIsAT(MCRegister RegIndex, SMLoc Loc) {
+ if (RegIndex && AssemblerOptions.back()->getATRegIndex() == RegIndex)
+ Warning(Loc, "used $at (currently $" + Twine(RegIndex.id()) +
") without \".set noat\"");
}
@@ -6214,7 +6210,7 @@ void MipsAsmParser::ConvertXWPOperands(MCInst &Inst,
(Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) &&
"Unexpected instruction!");
((MipsOperand &)*Operands[1]).addGPR32ZeroAsmRegOperands(Inst, 1);
- int NextReg = nextReg(((MipsOperand &)*Operands[1]).getGPR32Reg());
+ MCRegister NextReg = nextReg(((MipsOperand &)*Operands[1]).getGPR32Reg());
Inst.addOperand(MCOperand::createReg(NextReg));
((MipsOperand &)*Operands[2]).addMemOperands(Inst, 2);
}
@@ -6391,19 +6387,19 @@ bool MipsAsmParser::canUseATReg() {
return AssemblerOptions.back()->getATRegIndex() != 0;
}
-unsigned MipsAsmParser::getATReg(SMLoc Loc) {
+MCRegister MipsAsmParser::getATReg(SMLoc Loc) {
unsigned ATIndex = AssemblerOptions.back()->getATRegIndex();
if (ATIndex == 0) {
reportParseError(Loc,
"pseudo-instruction requires $at, which is not available");
return 0;
}
- unsigned AT = getReg(
+ MCRegister AT = getReg(
(isGP64bit()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, ATIndex);
return AT;
}
-unsigned MipsAsmParser::getReg(int RC, int RegNo) {
+MCRegister MipsAsmParser::getReg(int RC, int RegNo) {
return getContext().getRegisterInfo()->getRegClass(RC).getRegister(RegNo);
}
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
index b9a2af3341236..bd4c5d35ddfbe 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
@@ -147,7 +147,7 @@ inline static MCRegister getMSARegFromFReg(MCRegister Reg) {
else if (Reg >= Mips::D0_64 && Reg <= Mips::D31_64)
return Reg - Mips::D0_64 + Mips::W0;
else
- return Mips::NoRegister;
+ return MCRegister();
}
}
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp
index f861268c00158..e8b9746da467c 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp
@@ -46,7 +46,7 @@ void MipsELFStreamer::emitInstruction(const MCInst &Inst,
if (!Op.isReg())
continue;
- unsigned Reg = Op.getReg();
+ MCRegister Reg = Op.getReg();
RegInfoRecord->SetPhysRegUsed(Reg, MCRegInfo);
}
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
index 73ee44eec22cd..097b3cf8aa723 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -91,8 +91,8 @@ static void LowerLargeShift(MCInst& Inst) {
void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
// Encoding may be illegal !(rs < rt), but this situation is
// easily fixed.
- unsigned RegOp0 = Inst.getOperand(0).getReg();
- unsigned RegOp1 = Inst.getOperand(1).getReg();
+ MCRegister RegOp0 = Inst.getOperand(0).getReg();
+ MCRegister RegOp1 = Inst.getOperand(1).getReg();
unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0);
unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1);
@@ -724,7 +724,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (MO.isReg()) {
- unsigned Reg = MO.getReg();
+ MCRegister Reg = MO.getReg();
unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
return RegNo;
} else if (MO.isImm()) {
@@ -1033,7 +1033,7 @@ MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
// placed before memory operand (register + imm).
for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
- unsigned Reg = MI.getOperand(I).getReg();
+ MCRegister Reg = MI.getOperand(I).getReg();
unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
if (RegNo != 31)
res++;
@@ -1093,7 +1093,7 @@ MipsMCCodeEmitter::getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo,
MCOperand Op = MI.getOperand(OpNo);
assert(Op.isReg() && "Operand of movep is not a register!");
- switch (Op.getReg()) {
+ switch (Op.getReg().id()) {
default:
llvm_unreachable("Unknown register for movep!");
case Mips::ZERO: return 0;
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h
index 2722e34b3f624..94b2f412c8cdb 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h
@@ -19,7 +19,7 @@ static const Align MIPS_NACL_BUNDLE_ALIGN = Align(16);
bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
bool *IsStore = nullptr);
-bool baseRegNeedsLoadStoreMask(unsigned Reg);
+bool baseRegNeedsLoadStoreMask(MCRegister Reg);
// This function creates an MCELFStreamer for Mips NaCl.
MCELFStreamer *
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
index 8bd2b2ac231bf..3410726c8e553 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
@@ -97,7 +97,7 @@ class MipsNaClELFStreamer : public MipsELFStreamer {
}
}
- void emitMask(unsigned AddrReg, unsigned MaskReg,
+ void emitMask(MCRegister AddrReg, unsigned MaskReg,
const MCSubtargetInfo &STI) {
MCInst MaskInst;
MaskInst.setOpcode(Mips::AND);
@@ -110,7 +110,7 @@ class MipsNaClELFStreamer : public MipsELFStreamer {
// Sandbox indirect branch or return instruction by inserting mask operation
// before it.
void sandboxIndirectJump(const MCInst &MI, const MCSubtargetInfo &STI) {
- unsigned AddrReg = MI.getOperand(0).getReg();
+ MCRegister AddrReg = MI.getOperand(0).getReg();
emitBundleLock(false);
emitMask(AddrReg, IndirectBranchMaskReg, STI);
@@ -126,13 +126,13 @@ class MipsNaClELFStreamer : public MipsELFStreamer {
emitBundleLock(false);
if (MaskBefore) {
// Sandbox memory access.
- unsigned BaseReg = MI.getOperand(AddrIdx).getReg();
+ MCRegister BaseReg = MI.getOperand(AddrIdx).getReg();
emitMask(BaseReg, LoadStoreStackMaskReg, STI);
}
MipsELFStreamer::emitInstruction(MI, STI);
if (MaskAfter) {
// Sandbox SP change.
- unsigned SPReg = MI.getOperand(0).getReg();
+ MCRegister SPReg = MI.getOperand(0).getReg();
assert((Mips::SP == SPReg) && "Unexpected stack-pointer register.");
emitMask(SPReg, LoadStoreStackMaskReg, STI);
}
@@ -182,7 +182,7 @@ class MipsNaClELFStreamer : public MipsELFStreamer {
// Start the sandboxing sequence by emitting call.
emitBundleLock(true);
if (IsIndirectCall) {
- unsigned TargetReg = Inst.getOperand(1).getReg();
+ MCRegister TargetReg = Inst.getOperand(1).getReg();
emitMask(TargetReg, IndirectBranchMaskReg, STI);
}
MipsELFStreamer::emitInstruction(Inst, STI);
@@ -253,7 +253,7 @@ bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
}
}
-bool baseRegNeedsLoadStoreMask(unsigned Reg) {
+bool baseRegNeedsLoadStoreMask(MCRegister Reg) {
// The contents of SP and thread pointer register do not require masking.
return Reg != Mips::SP && Reg != Mips::T8;
}
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
index e547e62094404..670dc71b00e5f 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
@@ -81,8 +81,8 @@ void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
void MipsTargetStreamer::emitDirectiveOptionPic0() {}
void MipsTargetStreamer::emitDirectiveOptionPic2() {}
void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
-void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
- unsigned ReturnReg) {}
+void MipsTargetStreamer::emitFrame(MCRegister StackReg, unsigned StackSize,
+ MCRegister ReturnReg) {}
void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
}
@@ -173,7 +173,7 @@ void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
forbidModuleDirective();
}
-void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
+void MipsTargetStreamer::emitR(unsigned Opcode, MCRegister Reg0, SMLoc IDLoc,
const MCSubtargetInfo *STI) {
MCInst TmpInst;
TmpInst.setOpcode(Opcode);
@@ -182,7 +182,7 @@ void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
getStreamer().emitInstruction(TmpInst, *STI);
}
-void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
+void MipsTargetStreamer::emitRX(unsigned Opcode, MCRegister Reg0, MCOperand Op1,
SMLoc IDLoc, const MCSubtargetInfo *STI) {
MCInst TmpInst;
TmpInst.setOpcode(Opcode);
@@ -192,13 +192,14 @@ void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
getStreamer().emitInstruction(TmpInst, *STI);
}
-void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
+void MipsTargetStreamer::emitRI(unsigned Opcode, MCRegister Reg0, int32_t Imm,
SMLoc IDLoc, const MCSubtargetInfo *STI) {
emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
}
-void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
- SMLoc IDLoc, const MCSubtargetInfo *STI) {
+void MipsTargetStreamer::emitRR(unsigned Opcode, MCRegister Reg0,
+ MCRegister Reg1, SMLoc IDLoc,
+ const MCSubtargetInfo *STI) {
emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
}
@@ -212,8 +213,8 @@ void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
getStreamer().emitInstruction(TmpInst, *STI);
}
-void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
- MCOperand Op2, SMLoc IDLoc,
+void MipsTargetStreamer::emitRRX(unsigned Opcode, MCRegister Reg0,
+ MCRegister Reg1, MCOperand Op2, SMLoc IDLoc,
const MCSubtargetInfo *STI) {
MCInst TmpInst;
TmpInst.setOpcode(Opcode);
@@ -224,14 +225,15 @@ void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
getStreamer().emitInstruction(TmpInst, *STI);
}
-void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
- unsigned Reg2, SMLoc IDLoc,
+void MipsTargetStreamer::emitRRR(unsigned Opcode, MCRegister Reg0,
+ MCRegister Reg1, MCRegister Reg2, SMLoc IDLoc,
const MCSubtargetInfo *STI) {
emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
}
-void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
- unsigned Reg2, MCOperand Op3, SMLoc IDLoc,
+void MipsTargetStreamer::emitRRRX(unsigned Opcode, MCRegister Reg0,
+ MCRegister Reg1, MCRegister Reg2,
+ MCOperand Op3, SMLoc IDLoc,
const MCSubtargetInfo *STI) {
MCInst TmpInst;
TmpInst.setOpcode(Opcode);
@@ -243,14 +245,14 @@ void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
getStreamer().emitInstruction(TmpInst, *STI);
}
-void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
- int16_t Imm, SMLoc IDLoc,
+void MipsTargetStreamer::emitRRI(unsigned Opcode, MCRegister Reg0,
+ MCRegister Reg1, int16_t Imm, SMLoc IDLoc,
const MCSubtargetInfo *STI) {
emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
}
-void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
- unsigned Reg1, int16_t Imm0, int16_t Imm1,
+void MipsTargetStreamer::emitRRIII(unsigned Opcode, MCRegister Reg0,
+ MCRegister Reg1, int16_t Imm0, int16_t Imm1,
int16_t Imm2, SMLoc IDLoc,
const MCSubtargetInfo *STI) {
MCInst TmpInst;
@@ -264,14 +266,14 @@ void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
getStreamer().emitInstruction(TmpInst, *STI);
}
-void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
- unsigned TrgReg, bool Is64Bit,
+void MipsTargetStreamer::emitAddu(MCRegister DstReg, MCRegister SrcReg,
+ MCRegister TrgReg, bool Is64Bit,
const MCSubtargetInfo *STI) {
emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
STI);
}
-void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
+void MipsTargetStreamer::emitDSLL(MCRegister DstReg, MCRegister SrcReg,
int16_t ShiftAmount, SMLoc IDLoc,
const MCSubtargetInfo *STI) {
if (ShiftAmount >= 32) {
@@ -313,7 +315,7 @@ void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
/// Emit a store instruction with an immediate offset.
void MipsTargetStreamer::emitStoreWithImmOffset(
- unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
+ unsigned Opcode, MCRegister SrcReg, MCRegister BaseReg, int64_t Offset,
function_ref<unsigned()> GetATReg, SMLoc IDLoc,
const MCSubtargetInfo *STI) {
if (isInt<16>(Offset)) {
@@ -325,7 +327,7 @@ void MipsTargetStreamer::emitStoreWithImmOffset(
// add $at, $at, $8
// sw $8, %lo(offset)($at)
- unsigned ATReg = GetATReg();
+ MCRegister ATReg = GetATReg();
if (!ATReg)
return;
@@ -349,10 +351,9 @@ void MipsTargetStreamer::emitStoreWithImmOffset(
/// permitted to be the same register iff DstReg is distinct from BaseReg and
/// DstReg is a GPR. It is the callers responsibility to identify such cases
/// and pass the appropriate register in TmpReg.
-void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
- unsigned BaseReg, int64_t Offset,
- unsigned TmpReg, SMLoc IDLoc,
- const MCSubtargetInfo *STI) {
+void MipsTargetStreamer::emitLoadWithImmOffset(
+ unsigned Opcode, MCRegister DstReg, MCRegister BaseReg, int64_t Offset,
+ MCRegister TmpReg, SMLoc IDLoc, const MCSubtargetInfo *STI) {
if (isInt<16>(Offset)) {
emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
return;
@@ -519,8 +520,8 @@ void MipsTargetAsmStreamer::emitDirectiveInsn() {
OS << "\t.insn\n";
}
-void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
- unsigned ReturnReg) {
+void MipsTargetAsmStreamer::emitFrame(MCRegister StackReg, unsigned StackSize,
+ MCRegister ReturnReg) {
OS << "\t.frame\t$"
<< StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
<< StackSize << ",$"
@@ -1113,8 +1114,8 @@ void MipsTargetELFStreamer::emitDirectiveInsn() {
MEF.createPendingLabelRelocs();
}
-void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
- unsigned ReturnReg_) {
+void MipsTargetELFStreamer::emitFrame(MCRegister StackReg, unsigned StackSize,
+ MCRegister ReturnReg_) {
MCContext &Context = getStreamer().getAssembler().getContext();
const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
index 6b07999d862d9..b0b7b5dc7a31d 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -380,7 +380,7 @@ void MipsAsmPrinter::emitFrameDirective() {
const TargetRegisterInfo &RI = *MF->getSubtarget().getRegisterInfo();
Register stackReg = RI.getFrameRegister(*MF);
- unsigned returnReg = RI.getRARegister();
+ MCRegister returnReg = RI.getRARegister();
unsigned stackSize = MF->getFrameInfo().getStackSize();
getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
index c3e21e0ff7a0f..738fabea25bf7 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -70,7 +70,7 @@ void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
MIB.addReg(Mips::DSPEFI, Flag);
}
-unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
+MCRegister MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
uint64_t RegNum = RegIdx->getAsZExtVal();
return Mips::MSACtrlRegClass.getRegister(RegNum);
}
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
index 366c352d5cc0c..4122de7646f36 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
@@ -30,7 +30,7 @@ class MipsSEDAGToDAGISel : public MipsDAGToDAGISel {
void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
MachineFunction &MF);
- unsigned getMSACtrlReg(const SDValue RegIdx) const;
+ MCRegister getMSACtrlReg(const SDValue RegIdx) const;
bool replaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
diff --git a/llvm/lib/Target/Mips/MipsTargetStreamer.h b/llvm/lib/Target/Mips/MipsTargetStreamer.h
index 0603379d2e4fa..c73013baa4f05 100644
--- a/llvm/lib/Target/Mips/MipsTargetStreamer.h
+++ b/llvm/lib/Target/Mips/MipsTargetStreamer.h
@@ -58,8 +58,8 @@ class MipsTargetStreamer : public MCTargetStreamer {
virtual void emitDirectiveOptionPic0();
virtual void emitDirectiveOptionPic2();
virtual void emitDirectiveInsn();
- virtual void emitFrame(unsigned StackReg, unsigned StackSize,
- unsigned ReturnReg);
+ virtual void emitFrame(MCRegister StackReg, unsigned StackSize,
+ MCRegister ReturnReg);
virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff);
virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff);
@@ -118,30 +118,31 @@ class MipsTargetStreamer : public MCTargetStreamer {
virtual void emitDirectiveModuleGINV();
virtual void emitDirectiveModuleNoGINV();
- void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
+ void emitR(unsigned Opcode, MCRegister Reg0, SMLoc IDLoc,
const MCSubtargetInfo *STI);
void emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
const MCSubtargetInfo *STI);
- void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
+ void emitRX(unsigned Opcode, MCRegister Reg0, MCOperand Op1, SMLoc IDLoc,
const MCSubtargetInfo *STI);
- void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
+ void emitRI(unsigned Opcode, MCRegister Reg0, int32_t Imm, SMLoc IDLoc,
const MCSubtargetInfo *STI);
- void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
+ void emitRR(unsigned Opcode, MCRegister Reg0, MCRegister Reg1, SMLoc IDLoc,
const MCSubtargetInfo *STI);
- void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
+ void emitRRX(unsigned Opcode, MCRegister Reg0, MCRegister Reg1, MCOperand Op2,
SMLoc IDLoc, const MCSubtargetInfo *STI);
- void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
- SMLoc IDLoc, const MCSubtargetInfo *STI);
- void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
- MCOperand Op3, SMLoc IDLoc, const MCSubtargetInfo *STI);
- void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
+ void emitRRR(unsigned Opcode, MCRegister Reg0, MCRegister Reg1,
+ MCRegister Reg2, SMLoc IDLoc, const MCSubtargetInfo *STI);
+ void emitRRRX(unsigned Opcode, MCRegister Reg0, MCRegister Reg1,
+ MCRegister Reg2, MCOperand Op3, SMLoc IDLoc,
+ const MCSubtargetInfo *STI);
+ void emitRRI(unsigned Opcode, MCRegister Reg0, MCRegister Reg1, int16_t Imm,
SMLoc IDLoc, const MCSubtargetInfo *STI);
- void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
- int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
+ void emitRRIII(unsigned Opcode, MCRegister Reg0, MCRegister Reg1,
+ int16_t Imm0, int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
const MCSubtargetInfo *STI);
- void emitAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, bool Is64Bit,
- const MCSubtargetInfo *STI);
- void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
+ void emitAddu(MCRegister DstReg, MCRegister SrcReg, MCRegister TrgReg,
+ bool Is64Bit, const MCSubtargetInfo *STI);
+ void emitDSLL(MCRegister DstReg, MCRegister SrcReg, int16_t ShiftAmount,
SMLoc IDLoc, const MCSubtargetInfo *STI);
void emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
const MCSubtargetInfo *STI);
@@ -154,12 +155,13 @@ class MipsTargetStreamer : public MCTargetStreamer {
/// temporary and is only called when the assembler temporary is required. It
/// must handle the case where no assembler temporary is available (typically
/// by reporting an error).
- void emitStoreWithImmOffset(unsigned Opcode, unsigned SrcReg,
- unsigned BaseReg, int64_t Offset,
+ void emitStoreWithImmOffset(unsigned Opcode, MCRegister SrcReg,
+ MCRegister BaseReg, int64_t Offset,
function_ref<unsigned()> GetATReg, SMLoc IDLoc,
const MCSubtargetInfo *STI);
- void emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg, unsigned BaseReg,
- int64_t Offset, unsigned TmpReg, SMLoc IDLoc,
+ void emitLoadWithImmOffset(unsigned Opcode, MCRegister DstReg,
+ MCRegister BaseReg, int64_t Offset,
+ MCRegister TmpReg, SMLoc IDLoc,
const MCSubtargetInfo *STI);
void emitGPRestore(int Offset, SMLoc IDLoc, const MCSubtargetInfo *STI);
@@ -240,8 +242,8 @@ class MipsTargetAsmStreamer : public MipsTargetStreamer {
void emitDirectiveOptionPic0() override;
void emitDirectiveOptionPic2() override;
void emitDirectiveInsn() override;
- void emitFrame(unsigned StackReg, unsigned StackSize,
- unsigned ReturnReg) override;
+ void emitFrame(MCRegister StackReg, unsigned StackSize,
+ MCRegister ReturnReg) override;
void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override;
void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
@@ -340,8 +342,8 @@ class MipsTargetELFStreamer : public MipsTargetStreamer {
void emitDirectiveOptionPic0() override;
void emitDirectiveOptionPic2() override;
void emitDirectiveInsn() override;
- void emitFrame(unsigned StackReg, unsigned StackSize,
- unsigned ReturnReg) override;
+ void emitFrame(MCRegister StackReg, unsigned StackSize,
+ MCRegister ReturnReg) override;
void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override;
void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
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