[llvm] [llvm][ARM] Add a cortex-m4f alignment hazard recognizer (PR #126991)
Jon Roelofs via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 16 10:45:38 PST 2025
https://github.com/jroelofs updated https://github.com/llvm/llvm-project/pull/126991
>From ff3c3d8cc0edb1293be798b3ae2165d7a6e09380 Mon Sep 17 00:00:00 2001
From: Jon Roelofs <jonathan_roelofs at apple.com>
Date: Wed, 12 Feb 2025 09:01:38 -0800
Subject: [PATCH 01/11] [llvm][ARM] Add a cortex-m4f alignment hazard
recognizer
https://developer.arm.com/documentation/ka006138/latest
"A long sequence of T32 single-cycle floating-point instructions aligned on odd
halfword boundaries will experience a performance drop. Specifically, one stall
cycle is inserted for every three instructions executed."
To avoid this pipeline hazard, we insert a new hazard recognizer that counts
instruction alignments and informs the instruction scheduler of the stalls. We
run the same hazard recognizer very late in the pass pipeline in order to
inform nop placement, and fix up the alignment of single-cycle T32
floating-point instructions to even halfword boundaries.
rdar://139016056
---
llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 5 +
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 33 +++
llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 6 +
llvm/lib/Target/ARM/ARMHazardRecognizer.cpp | 161 ++++++++++++++
llvm/lib/Target/ARM/ARMHazardRecognizer.h | 44 ++++
llvm/lib/Target/ARM/ARMInstrInfo.h | 5 +
llvm/lib/Target/ARM/ARMProcessors.td | 3 +
llvm/lib/Target/ARM/ARMSubtarget.cpp | 1 +
llvm/lib/Target/ARM/ARMSubtarget.h | 1 +
llvm/lib/Target/ARM/ARMTargetMachine.cpp | 10 +
llvm/test/CodeGen/ARM/O3-pipeline.ll | 1 +
.../ARM/cortex-m4f-alignment-hazard.mir | 207 ++++++++++++++++++
12 files changed, 477 insertions(+)
create mode 100644 llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index b8772e1665f8a..83d6b365605b6 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -14,6 +14,7 @@
#include "ARMAsmPrinter.h"
#include "ARM.h"
#include "ARMConstantPoolValue.h"
+#include "ARMInstrInfo.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMTargetMachine.h"
#include "ARMTargetObjectFile.h"
@@ -1445,6 +1446,10 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
InConstantPool = false;
}
+ if (MI->getAsmPrinterFlag(
+ MachineInstr::CommentFlag(ARM::M4F_ALIGNMENT_HAZARD)))
+ OutStreamer->AddComment("cortex-m4f alignment hazard");
+
// Emit unwinding stuff for frame-related instructions
if (Subtarget->isTargetEHABICompatible() &&
MI->getFlag(MachineInstr::FrameSetup))
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 839b7e81f8998..78c3d90854fca 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -151,6 +151,11 @@ ScheduleHazardRecognizer *ARMBaseInstrInfo::CreateTargetMIHazardRecognizer(
MHR->AddHazardRecognizer(
std::make_unique<ARMBankConflictHazardRecognizer>(DAG, 0x4, true));
+ if (Subtarget.isCortexM4() && !DAG->hasVRegLiveness())
+ MHR->AddHazardRecognizer(
+ std::make_unique<ARMCortexM4AlignmentHazardRecognizer>(
+ DAG->MF.getSubtarget()));
+
// Not inserting ARMHazardRecognizerFPMLx because that would change
// legacy behavior
@@ -168,12 +173,25 @@ CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
if (Subtarget.isThumb2() || Subtarget.hasVFP2Base())
MHR->AddHazardRecognizer(std::make_unique<ARMHazardRecognizerFPMLx>());
+ if (Subtarget.isCortexM4())
+ MHR->AddHazardRecognizer(
+ std::make_unique<ARMCortexM4AlignmentHazardRecognizer>(
+ DAG->MF.getSubtarget()));
+
auto BHR = TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
if (BHR)
MHR->AddHazardRecognizer(std::unique_ptr<ScheduleHazardRecognizer>(BHR));
return MHR;
}
+ScheduleHazardRecognizer *ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer(
+ const MachineFunction &MF) const {
+ if (!Subtarget.isCortexM4())
+ return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(MF);
+
+ return new ARMCortexM4AlignmentHazardRecognizer(MF.getSubtarget());
+}
+
MachineInstr *
ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
LiveIntervals *LIS) const {
@@ -5455,6 +5473,21 @@ bool ARMBaseInstrInfo::hasNOP() const {
return Subtarget.hasFeature(ARM::HasV6KOps);
}
+void ARMBaseInstrInfo::insertNoop(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI) const {
+ DebugLoc DL;
+ if (hasNOP()) {
+ BuildMI(MBB, MI, DL, get(ARM::HINT)).addImm(0).addImm(ARMCC::AL).addImm(0);
+ } else {
+ BuildMI(MBB, MI, DL, get(ARM::MOVr))
+ .addReg(ARM::R0)
+ .addReg(ARM::R0)
+ .addImm(ARMCC::AL)
+ .addReg(0)
+ .addReg(0);
+ }
+}
+
bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
if (MI->getNumOperands() < 4)
return true;
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index ae760e881e7fa..396dd8d3b6627 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -121,6 +121,9 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
// Return whether the target has an explicit NOP encoding.
bool hasNOP() const;
+ void insertNoop(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI) const override;
+
// Return the non-pre/post incrementing version of 'Opc'. Return 0
// if there is not such an opcode.
virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
@@ -143,6 +146,9 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
const ScheduleDAG *DAG) const override;
+ ScheduleHazardRecognizer *
+ CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
+
// Branch analysis.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
diff --git a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
index e78f228a912c0..3df8317cedb79 100644
--- a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
+++ b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
@@ -8,13 +8,18 @@
#include "ARMHazardRecognizer.h"
#include "ARMBaseInstrInfo.h"
+#include "ARMBaseRegisterInfo.h"
+#include "ARMInstrInfo.h"
#include "ARMSubtarget.h"
+#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Support/CommandLine.h"
+#include <algorithm>
using namespace llvm;
@@ -266,3 +271,159 @@ void ARMBankConflictHazardRecognizer::EmitInstruction(SUnit *SU) {
void ARMBankConflictHazardRecognizer::AdvanceCycle() { Accesses.clear(); }
void ARMBankConflictHazardRecognizer::RecedeCycle() { Accesses.clear(); }
+
+#define DEBUG_TYPE "cortex-m4-alignment-hazard-rec"
+
+STATISTIC(NumNoops, "Number of noops inserted");
+
+static cl::opt<bool> LoopsOnly(DEBUG_TYPE "-loops-only", cl::Hidden,
+ cl::init(true),
+ cl::desc("Emit nops only in loops"));
+
+static cl::opt<bool>
+ InnermostLoopsOnly(DEBUG_TYPE "-innermost-loops-only", cl::Hidden,
+ cl::init(true),
+ cl::desc("Emit noops only in innermost loops"));
+
+void ARMCortexM4AlignmentHazardRecognizer::Reset() { Offset = 0; }
+
+ARMCortexM4AlignmentHazardRecognizer::ARMCortexM4AlignmentHazardRecognizer(
+ const MCSubtargetInfo &STI)
+ : STI(STI), MBB(nullptr), MF(nullptr), Offset(0), Advanced(false),
+ EmittingNoop(false) {
+ MaxLookAhead = 1;
+}
+
+void ARMCortexM4AlignmentHazardRecognizer::EmitInstruction(SUnit *SU) {
+ if (!SU->isInstr())
+ return;
+
+ MachineInstr *MI = SU->getInstr();
+ assert(MI);
+ return EmitInstruction(MI);
+}
+
+void ARMCortexM4AlignmentHazardRecognizer::EmitInstruction(MachineInstr *MI) {
+ if (MI->isDebugInstr())
+ return;
+
+ unsigned Size = MI->getDesc().getSize();
+ Offset += Size;
+
+ // If the previous instruction had a hazard, then we're inserting a nop. Mark
+ // it with an AsmPrinter comment.
+ if (EmittingNoop)
+ if (MachineInstr *Prev = MI->getPrevNode())
+ Prev->setAsmPrinterFlag(ARM::M4F_ALIGNMENT_HAZARD);
+
+ EmittingNoop = false;
+}
+
+ScheduleHazardRecognizer::HazardType
+ARMCortexM4AlignmentHazardRecognizer::getHazardType(SUnit *SU,
+ int /*Ignored*/) {
+ if (!SU->isInstr())
+ return HazardType::NoHazard;
+
+ MachineInstr *MI = SU->getInstr();
+ assert(MI);
+ return getHazardTypeAssumingOffset(MI, Offset);
+}
+
+ScheduleHazardRecognizer::HazardType
+ARMCortexM4AlignmentHazardRecognizer::getHazardTypeAssumingOffset(
+ MachineInstr *MI, size_t AssumedOffset) {
+ if (Advanced) {
+ Advanced = false;
+ return HazardType::NoHazard;
+ }
+
+ if (AssumedOffset % 4 == 0)
+ return HazardType::NoHazard;
+
+ const MCSchedModel &SCModel = STI.getSchedModel();
+ const MachineFunction *MF = MI->getParent()->getParent();
+ const ARMBaseInstrInfo &TII =
+ *static_cast<const ARMBaseInstrInfo *>(MF->getSubtarget().getInstrInfo());
+ int Latency = SCModel.computeInstrLatency<MCSubtargetInfo, MCInstrInfo,
+ InstrItineraryData, MachineInstr>(
+ STI, TII, *MI);
+ if (!Latency)
+ return HazardType::NoHazard;
+
+ const MCInstrDesc &MCID = MI->getDesc();
+ unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
+
+ bool SingleCycleFP =
+ Latency == 1 && (Domain & (ARMII::DomainNEON | ARMII::DomainVFP));
+ if (SingleCycleFP)
+ return HazardType::NoopHazard;
+
+ if (MCID.getSize() == 4 && (MI->mayLoad() || MI->mayStore()))
+ return HazardType::NoopHazard;
+
+ return HazardType::NoHazard;
+}
+
+void ARMCortexM4AlignmentHazardRecognizer::AdvanceCycle() { Advanced = true; }
+void ARMCortexM4AlignmentHazardRecognizer::RecedeCycle() {}
+
+void ARMCortexM4AlignmentHazardRecognizer::EmitNoop() { Offset += 2; }
+
+unsigned ARMCortexM4AlignmentHazardRecognizer::PreEmitNoops(SUnit *SU) {
+ if (!SU->isInstr())
+ return 0;
+
+ MachineInstr *MI = SU->getInstr();
+ assert(MI);
+ return PreEmitNoops(MI);
+}
+
+unsigned ARMCortexM4AlignmentHazardRecognizer::PreEmitNoops(MachineInstr *MI) {
+ const MachineBasicBlock *Parent = MI->getParent();
+ if (Parent != MBB) {
+ Offset = 0;
+ MBB = Parent;
+ }
+
+ LLVM_DEBUG(MI->dump());
+
+ if (LoopsOnly) {
+ // This optimization is likely only critical in loops. Try to save code size
+ // elsewhere by avoiding it when we're not in an innermost loop.
+ if (const MachineLoop *Loop = getLoopFor(MI)) {
+ if (InnermostLoopsOnly && !Loop->isInnermost()) {
+ LLVM_DEBUG(dbgs() << "\toffset=0x" << utohexstr(Offset)
+ << "\n\tnot in an innermost loop\n");
+ return 0;
+ }
+ } else if (LoopsOnly) {
+ LLVM_DEBUG(dbgs() << "\toffset=0x" << utohexstr(Offset)
+ << "\n\tnot in a loop\n");
+ return 0;
+ }
+ }
+
+ if (HazardType::NoopHazard == getHazardTypeAssumingOffset(MI, Offset)) {
+ EmittingNoop = true;
+ NumNoops++;
+ LLVM_DEBUG(dbgs() << "\toffset=0x" << utohexstr(Offset)
+ << "\n\thas an alignment hazard, and requires a noop\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+const MachineLoop *
+ARMCortexM4AlignmentHazardRecognizer::getLoopFor(MachineInstr *MI) {
+ // Calculate and cache the MachineLoopInfo.
+ MachineFunction *ParentMF = MI->getParent()->getParent();
+ if (MF != ParentMF) {
+ MF = ParentMF;
+ MDT = MachineDominatorTree(*MF);
+ MLI.~MachineLoopInfo();
+ new (&MLI) MachineLoopInfo(MDT);
+ }
+ return MLI.getLoopFor(MI->getParent());
+}
\ No newline at end of file
diff --git a/llvm/lib/Target/ARM/ARMHazardRecognizer.h b/llvm/lib/Target/ARM/ARMHazardRecognizer.h
index b9ac3555c2bc3..5e2c4e7bef27a 100644
--- a/llvm/lib/Target/ARM/ARMHazardRecognizer.h
+++ b/llvm/lib/Target/ARM/ARMHazardRecognizer.h
@@ -16,6 +16,8 @@
#include "ARMBaseInstrInfo.h"
#include "llvm/ADT/BitmaskEnum.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/Support/DataTypes.h"
#include <initializer_list>
@@ -63,6 +65,48 @@ class ARMBankConflictHazardRecognizer : public ScheduleHazardRecognizer {
inline HazardType CheckOffsets(unsigned O0, unsigned O1);
};
+/**
+ Hazards related to alignment of single-cycle fp instructions on cortex-m4f.
+
+ https://developer.arm.com/documentation/ka006138/latest
+
+ "A long sequence of T32 single-cycle floating-point instructions aligned on
+ odd halfword boundaries will experience a performance drop. Specifically, one
+ stall cycle is inserted for every three instructions executed."
+*/
+class ARMCortexM4AlignmentHazardRecognizer : public ScheduleHazardRecognizer {
+ const MCSubtargetInfo &STI;
+ const MachineBasicBlock *MBB;
+ MachineDominatorTree MDT;
+ MachineLoopInfo MLI;
+ MachineFunction *MF;
+ size_t Offset;
+ bool Advanced;
+ bool EmittingNoop;
+
+public:
+ ARMCortexM4AlignmentHazardRecognizer(const MCSubtargetInfo &STI);
+
+ void Reset() override;
+
+ void AdvanceCycle() override;
+ void RecedeCycle() override;
+ void EmitNoop() override;
+
+ void EmitInstruction(SUnit *SU) override;
+ void EmitInstruction(MachineInstr *MI) override;
+
+ HazardType getHazardType(SUnit *SU, int Stalls = 0) override;
+ HazardType getHazardType(MachineInstr *MI);
+ HazardType getHazardTypeAssumingOffset(MachineInstr *MI, size_t Offset);
+
+ unsigned PreEmitNoops(SUnit *SU) override;
+ unsigned PreEmitNoops(MachineInstr *MI) override;
+
+private:
+ const MachineLoop *getLoopFor(MachineInstr *MI);
+};
+
} // end namespace llvm
#endif
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.h b/llvm/lib/Target/ARM/ARMInstrInfo.h
index 178d7a2c630e4..6e988a1113583 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.h
@@ -41,6 +41,11 @@ class ARMInstrInfo : public ARMBaseInstrInfo {
void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
};
+namespace ARM {
+enum AsmComments {
+ M4F_ALIGNMENT_HAZARD = MachineInstr::TAsmComments,
+};
+} // namespace ARM
}
#endif
diff --git a/llvm/lib/Target/ARM/ARMProcessors.td b/llvm/lib/Target/ARM/ARMProcessors.td
index 7453727a7cff0..046a67c0c472d 100644
--- a/llvm/lib/Target/ARM/ARMProcessors.td
+++ b/llvm/lib/Target/ARM/ARMProcessors.td
@@ -99,6 +99,8 @@ def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
"Cortex-M3 ARM processors", []>;
def ProcM55 : SubtargetFeature<"m55", "ARMProcFamily", "CortexM55",
"Cortex-M55 ARM processors", []>;
+def ProcM4 : SubtargetFeature<"m4", "ARMProcFamily", "CortexM4",
+ "Cortex-M4 ARM processors", []>;
def ProcM7 : SubtargetFeature<"m7", "ARMProcFamily", "CortexM7",
"Cortex-M7 ARM processors", []>;
def ProcM85 : SubtargetFeature<"m85", "ARMProcFamily", "CortexM85",
@@ -340,6 +342,7 @@ def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m,
FeatureHasNoBranchPredictor]>;
def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em,
+ ProcM4,
FeatureVFP4_D16_SP,
FeaturePreferBranchAlign32,
FeatureHasSlowFPVMLx,
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 893084785e6f0..a1fbb387cce09 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -289,6 +289,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
case CortexA78C:
case CortexA510:
case CortexA710:
+ case CortexM4:
case CortexR4:
case CortexR5:
case CortexR7:
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index 7329d3f2055f0..86f3ca61418bf 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -292,6 +292,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
bool isSwift() const { return ARMProcFamily == Swift; }
bool isCortexM3() const { return ARMProcFamily == CortexM3; }
bool isCortexM55() const { return ARMProcFamily == CortexM55; }
+ bool isCortexM4() const { return ARMProcFamily == CortexM4; }
bool isCortexM7() const { return ARMProcFamily == CortexM7; }
bool isCortexM85() const { return ARMProcFamily == CortexM85; }
bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 98bdf310dea91..a988c2e3269fa 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -78,6 +78,10 @@ static cl::opt<cl::boolOrDefault>
EnableGlobalMerge("arm-global-merge", cl::Hidden,
cl::desc("Enable the global merge pass"));
+static cl::opt<cl::boolOrDefault> EnablePostRAHazardRecognizer(
+ "arm-postra-hazard-recognizer", cl::Hidden,
+ cl::desc("Enable the post-ra hazard recognizer"));
+
namespace llvm {
void initializeARMExecutionDomainFixPass(PassRegistry&);
}
@@ -622,6 +626,12 @@ void ARMPassConfig::addPreEmitPass2() {
// Identify valid eh continuation targets for Windows EHCont Guard.
addPass(createEHContGuardCatchretPass());
}
+
+ // Enable the hazard recognizer for cortex-m4f at -O2 or higher.
+ if ((EnablePostRAHazardRecognizer == cl::BOU_UNSET &&
+ CodeGenOptLevel::Default <= getOptLevel()) ||
+ EnablePostRAHazardRecognizer == cl::BOU_TRUE)
+ addPass(&PostRAHazardRecognizerID);
}
yaml::MachineFunctionInfo *
diff --git a/llvm/test/CodeGen/ARM/O3-pipeline.ll b/llvm/test/CodeGen/ARM/O3-pipeline.ll
index 1840b5ce46c6f..a3930c349b5d4 100644
--- a/llvm/test/CodeGen/ARM/O3-pipeline.ll
+++ b/llvm/test/CodeGen/ARM/O3-pipeline.ll
@@ -213,6 +213,7 @@
; CHECK-NEXT: Machine Natural Loop Construction
; CHECK-NEXT: ReachingDefAnalysis
; CHECK-NEXT: ARM Low Overhead Loops pass
+; CHECK-NEXT: Post RA hazard recognizer
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: ARM Assembly Printer
diff --git a/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir b/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir
new file mode 100644
index 0000000000000..7d8f6d1f7dacb
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir
@@ -0,0 +1,207 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck %s --check-prefixes=CHECK,DEFAULT
+# RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s -cortex-m4-alignment-hazard-rec-innermost-loops-only=0 | FileCheck %s --check-prefixes=CHECK,ANY-LOOPS
+# RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s -cortex-m4-alignment-hazard-rec-loops-only=0 | FileCheck %s --check-prefixes=CHECK,ANY-BLOCK
+
+---
+name: alignment_hazards_in_double_loop
+alignment: 4
+body: |
+ ; DEFAULT-LABEL: name: alignment_hazards_in_double_loop
+ ; DEFAULT: bb.0 (align 4):
+ ; DEFAULT-NEXT: successors: %bb.1(0x80000000)
+ ; DEFAULT-NEXT: {{ $}}
+ ; DEFAULT-NEXT: bb.1 (align 4):
+ ; DEFAULT-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; DEFAULT-NEXT: {{ $}}
+ ; DEFAULT-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; DEFAULT-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
+ ; DEFAULT-NEXT: {{ $}}
+ ; DEFAULT-NEXT: bb.2 (align 4):
+ ; DEFAULT-NEXT: successors: %bb.0(0x40000000), %bb.3(0x40000000)
+ ; DEFAULT-NEXT: {{ $}}
+ ; DEFAULT-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; DEFAULT-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
+ ; DEFAULT-NEXT: {{ $}}
+ ; DEFAULT-NEXT: bb.3:
+ ; DEFAULT-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; DEFAULT-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc
+ ;
+ ; ANY-LOOPS-LABEL: name: alignment_hazards_in_double_loop
+ ; ANY-LOOPS: bb.0 (align 4):
+ ; ANY-LOOPS-NEXT: successors: %bb.1(0x80000000)
+ ; ANY-LOOPS-NEXT: {{ $}}
+ ; ANY-LOOPS-NEXT: bb.1 (align 4):
+ ; ANY-LOOPS-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; ANY-LOOPS-NEXT: {{ $}}
+ ; ANY-LOOPS-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
+ ; ANY-LOOPS-NEXT: {{ $}}
+ ; ANY-LOOPS-NEXT: bb.2 (align 4):
+ ; ANY-LOOPS-NEXT: successors: %bb.0(0x40000000), %bb.3(0x40000000)
+ ; ANY-LOOPS-NEXT: {{ $}}
+ ; ANY-LOOPS-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
+ ; ANY-LOOPS-NEXT: {{ $}}
+ ; ANY-LOOPS-NEXT: bb.3:
+ ; ANY-LOOPS-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc
+ ;
+ ; ANY-BLOCK-LABEL: name: alignment_hazards_in_double_loop
+ ; ANY-BLOCK: bb.0 (align 4):
+ ; ANY-BLOCK-NEXT: successors: %bb.1(0x80000000)
+ ; ANY-BLOCK-NEXT: {{ $}}
+ ; ANY-BLOCK-NEXT: bb.1 (align 4):
+ ; ANY-BLOCK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; ANY-BLOCK-NEXT: {{ $}}
+ ; ANY-BLOCK-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
+ ; ANY-BLOCK-NEXT: {{ $}}
+ ; ANY-BLOCK-NEXT: bb.2 (align 4):
+ ; ANY-BLOCK-NEXT: successors: %bb.0(0x40000000), %bb.3(0x40000000)
+ ; ANY-BLOCK-NEXT: {{ $}}
+ ; ANY-BLOCK-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
+ ; ANY-BLOCK-NEXT: {{ $}}
+ ; ANY-BLOCK-NEXT: bb.3:
+ ; ANY-BLOCK-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc
+ bb.0 (align 4):
+ successors: %bb.1
+
+ bb.1 (align 4):
+ successors: %bb.1, %bb.2
+
+ renamable $s2 = VLDRS renamable $r3, 4, 14, $noreg
+ renamable $r2 = t2LSRri renamable $lr, 1, 14, $noreg, $noreg
+ renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14, $noreg
+ $s2 = VMOVSR $r1, 14, $noreg
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ $s2 = VMOVSR $r1, 14, $noreg
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ $s2 = VMOVSR $r1, 14, $noreg
+ renamable $s6 = VLDRS renamable $r3, 6, 14, $noreg
+ tBcc %bb.1, 1, killed $cpsr
+
+ bb.2 (align 4):
+ successors: %bb.0, %bb.3
+
+ renamable $s2 = VLDRS renamable $r3, 4, 14, $noreg
+ renamable $r2 = t2LSRri renamable $lr, 1, 14, $noreg, $noreg
+ renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14, $noreg
+ $s2 = VMOVSR $r1, 14, $noreg
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ $s2 = VMOVSR $r1, 14, $noreg
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ $s2 = VMOVSR $r1, 14, $noreg
+ renamable $s6 = VLDRS renamable $r3, 6, 14, $noreg
+ tBcc %bb.0, 1, killed $cpsr
+
+ bb.3:
+ renamable $s2 = VLDRS renamable $r3, 4, 14, $noreg
+ renamable $r2 = t2LSRri renamable $lr, 1, 14, $noreg, $noreg
+ renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14, $noreg
+ $s2 = VMOVSR $r1, 14, $noreg
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ $s2 = VMOVSR $r1, 14, $noreg
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ $s2 = VMOVSR $r1, 14, $noreg
+ renamable $s6 = VLDRS renamable $r3, 6, 14, $noreg
+ tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc
+...
>From 4f0950105e670334e71bfcb9e31f9fd81f1a1bad Mon Sep 17 00:00:00 2001
From: Jon Roelofs <jonathan_roelofs at apple.com>
Date: Thu, 13 Feb 2025 09:10:03 -0800
Subject: [PATCH 02/11] remove unused CHECK prefix
---
llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir b/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir
index 7d8f6d1f7dacb..ca3b3d6194a44 100644
--- a/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir
+++ b/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck %s --check-prefixes=CHECK,DEFAULT
-# RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s -cortex-m4-alignment-hazard-rec-innermost-loops-only=0 | FileCheck %s --check-prefixes=CHECK,ANY-LOOPS
-# RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s -cortex-m4-alignment-hazard-rec-loops-only=0 | FileCheck %s --check-prefixes=CHECK,ANY-BLOCK
+# RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck %s --check-prefix=DEFAULT
+# RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s -cortex-m4-alignment-hazard-rec-innermost-loops-only=0 | FileCheck %s --check-prefix=ANY-LOOPS
+# RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s -cortex-m4-alignment-hazard-rec-loops-only=0 | FileCheck %s --check-prefix=ANY-BLOCK
---
name: alignment_hazards_in_double_loop
>From 18e4ae5a2b2bd6ce474e98fb17302f490c587074 Mon Sep 17 00:00:00 2001
From: Jon Roelofs <jonathan_roelofs at apple.com>
Date: Thu, 13 Feb 2025 09:10:23 -0800
Subject: [PATCH 03/11] s/HINT/tHINT/g
---
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 +-
.../ARM/cortex-m4f-alignment-hazard.mir | 24 +++++++++----------
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 78c3d90854fca..ed0044b6e311d 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -5477,7 +5477,7 @@ void ARMBaseInstrInfo::insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
DebugLoc DL;
if (hasNOP()) {
- BuildMI(MBB, MI, DL, get(ARM::HINT)).addImm(0).addImm(ARMCC::AL).addImm(0);
+ BuildMI(MBB, MI, DL, get(ARM::tHINT)).addImm(0).addImm(ARMCC::AL).addImm(0);
} else {
BuildMI(MBB, MI, DL, get(ARM::MOVr))
.addReg(ARM::R0)
diff --git a/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir b/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir
index ca3b3d6194a44..ca33c79420670 100644
--- a/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir
+++ b/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir
@@ -17,10 +17,10 @@ body: |
; DEFAULT-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
; DEFAULT-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; DEFAULT-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; DEFAULT-NEXT: tHINT 0, 14 /* CC::al */, 0
; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; DEFAULT-NEXT: tHINT 0, 14 /* CC::al */, 0
; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
@@ -66,10 +66,10 @@ body: |
; ANY-LOOPS-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; ANY-LOOPS-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-LOOPS-NEXT: tHINT 0, 14 /* CC::al */, 0
; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-LOOPS-NEXT: tHINT 0, 14 /* CC::al */, 0
; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
@@ -83,10 +83,10 @@ body: |
; ANY-LOOPS-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; ANY-LOOPS-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-LOOPS-NEXT: tHINT 0, 14 /* CC::al */, 0
; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-LOOPS-NEXT: tHINT 0, 14 /* CC::al */, 0
; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
@@ -117,10 +117,10 @@ body: |
; ANY-BLOCK-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; ANY-BLOCK-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
@@ -134,10 +134,10 @@ body: |
; ANY-BLOCK-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; ANY-BLOCK-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
@@ -149,10 +149,10 @@ body: |
; ANY-BLOCK-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; ANY-BLOCK-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: HINT 0, 14 /* CC::al */, 0
+ ; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
>From 1be7e60f6825f5759592caac4deb12a90b3e4974 Mon Sep 17 00:00:00 2001
From: Jon Roelofs <jonathan_roelofs at apple.com>
Date: Thu, 13 Feb 2025 11:19:12 -0800
Subject: [PATCH 04/11] turn off nop insertion at -Oz
---
llvm/lib/Target/ARM/ARMHazardRecognizer.cpp | 4 +
.../ARM/cortex-m4f-alignment-hazard.mir | 180 ++++++++++++++++++
2 files changed, 184 insertions(+)
diff --git a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
index 3df8317cedb79..5c97cbfad867d 100644
--- a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
+++ b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
@@ -338,6 +338,10 @@ ARMCortexM4AlignmentHazardRecognizer::getHazardTypeAssumingOffset(
return HazardType::NoHazard;
}
+ const Function &F = MI->getParent()->getParent()->getFunction();
+ if (F.hasMinSize())
+ return HazardType::NoHazard;
+
if (AssumedOffset % 4 == 0)
return HazardType::NoHazard;
diff --git a/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir b/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir
index ca33c79420670..ed0bc0b755b97 100644
--- a/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir
+++ b/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir
@@ -2,7 +2,26 @@
# RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck %s --check-prefix=DEFAULT
# RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s -cortex-m4-alignment-hazard-rec-innermost-loops-only=0 | FileCheck %s --check-prefix=ANY-LOOPS
# RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s -cortex-m4-alignment-hazard-rec-loops-only=0 | FileCheck %s --check-prefix=ANY-BLOCK
+--- |
+ define void @alignment_hazards_in_double_loop() {
+ entry:
+ ret void
+ }
+ define void @has_minsize() #0 {
+ entry:
+ ret void
+ }
+
+ define void @has_optsize() #1 {
+ entry:
+ ret void
+ }
+
+ attributes #0 = { minsize }
+ attributes #1 = { optsize }
+
+...
---
name: alignment_hazards_in_double_loop
alignment: 4
@@ -205,3 +224,164 @@ body: |
renamable $s6 = VLDRS renamable $r3, 6, 14, $noreg
tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc
...
+---
+name: has_minsize
+alignment: 4
+body: |
+ ; DEFAULT-LABEL: name: has_minsize
+ ; DEFAULT: bb.0 (align 4):
+ ; DEFAULT-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; DEFAULT-NEXT: {{ $}}
+ ; DEFAULT-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; DEFAULT-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
+ ; DEFAULT-NEXT: {{ $}}
+ ; DEFAULT-NEXT: bb.1:
+ ; DEFAULT-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc
+ ;
+ ; ANY-LOOPS-LABEL: name: has_minsize
+ ; ANY-LOOPS: bb.0 (align 4):
+ ; ANY-LOOPS-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; ANY-LOOPS-NEXT: {{ $}}
+ ; ANY-LOOPS-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
+ ; ANY-LOOPS-NEXT: {{ $}}
+ ; ANY-LOOPS-NEXT: bb.1:
+ ; ANY-LOOPS-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc
+ ;
+ ; ANY-BLOCK-LABEL: name: has_minsize
+ ; ANY-BLOCK: bb.0 (align 4):
+ ; ANY-BLOCK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; ANY-BLOCK-NEXT: {{ $}}
+ ; ANY-BLOCK-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
+ ; ANY-BLOCK-NEXT: {{ $}}
+ ; ANY-BLOCK-NEXT: bb.1:
+ ; ANY-BLOCK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc
+ bb.0 (align 4):
+ successors: %bb.0, %bb.1
+
+ renamable $s2 = VLDRS renamable $r3, 4, 14, $noreg
+ renamable $r2 = t2LSRri renamable $lr, 1, 14, $noreg, $noreg
+ renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14, $noreg
+ $s2 = VMOVSR $r1, 14, $noreg
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ $s2 = VMOVSR $r1, 14, $noreg
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ $s2 = VMOVSR $r1, 14, $noreg
+ renamable $s6 = VLDRS renamable $r3, 6, 14, $noreg
+ tBcc %bb.0, 1, killed $cpsr
+
+ bb.1:
+ tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc
+...
+---
+name: has_optsize
+alignment: 4
+body: |
+ ; DEFAULT-LABEL: name: has_optsize
+ ; DEFAULT: bb.0 (align 4):
+ ; DEFAULT-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; DEFAULT-NEXT: {{ $}}
+ ; DEFAULT-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; DEFAULT-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: tHINT 0, 14 /* CC::al */, 0
+ ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: tHINT 0, 14 /* CC::al */, 0
+ ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
+ ; DEFAULT-NEXT: {{ $}}
+ ; DEFAULT-NEXT: bb.1:
+ ; DEFAULT-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc
+ ;
+ ; ANY-LOOPS-LABEL: name: has_optsize
+ ; ANY-LOOPS: bb.0 (align 4):
+ ; ANY-LOOPS-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; ANY-LOOPS-NEXT: {{ $}}
+ ; ANY-LOOPS-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: tHINT 0, 14 /* CC::al */, 0
+ ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: tHINT 0, 14 /* CC::al */, 0
+ ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
+ ; ANY-LOOPS-NEXT: {{ $}}
+ ; ANY-LOOPS-NEXT: bb.1:
+ ; ANY-LOOPS-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc
+ ;
+ ; ANY-BLOCK-LABEL: name: has_optsize
+ ; ANY-BLOCK: bb.0 (align 4):
+ ; ANY-BLOCK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; ANY-BLOCK-NEXT: {{ $}}
+ ; ANY-BLOCK-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
+ ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
+ ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
+ ; ANY-BLOCK-NEXT: {{ $}}
+ ; ANY-BLOCK-NEXT: bb.1:
+ ; ANY-BLOCK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc
+ bb.0 (align 4):
+ successors: %bb.0, %bb.1
+
+ renamable $s2 = VLDRS renamable $r3, 4, 14, $noreg
+ renamable $r2 = t2LSRri renamable $lr, 1, 14, $noreg, $noreg
+ renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14, $noreg
+ $s2 = VMOVSR $r1, 14, $noreg
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ $s2 = VMOVSR $r1, 14, $noreg
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ $s2 = VMOVSR $r1, 14, $noreg
+ renamable $s6 = VLDRS renamable $r3, 6, 14, $noreg
+ tBcc %bb.0, 1, killed $cpsr
+
+ bb.1:
+ tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc
>From 90bfaaacdd4f8f116a9c256d40e99dc3d751e1e3 Mon Sep 17 00:00:00 2001
From: Jon Roelofs <jonathan_roelofs at apple.com>
Date: Thu, 13 Feb 2025 11:24:18 -0800
Subject: [PATCH 05/11] cite docs on the load/store alignment issue
---
llvm/lib/Target/ARM/ARMHazardRecognizer.cpp | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
index 5c97cbfad867d..51c8e02f1f1e1 100644
--- a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
+++ b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
@@ -358,11 +358,21 @@ ARMCortexM4AlignmentHazardRecognizer::getHazardTypeAssumingOffset(
const MCInstrDesc &MCID = MI->getDesc();
unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
+ // https://developer.arm.com/documentation/ka006138/latest
+ //
+ // "A long sequence of T32 single-cycle floating-point instructions aligned on
+ // odd halfword boundaries will experience a performance drop. Specifically,
+ // one stall cycle is inserted for every three instructions executed."
bool SingleCycleFP =
Latency == 1 && (Domain & (ARMII::DomainNEON | ARMII::DomainVFP));
if (SingleCycleFP)
return HazardType::NoopHazard;
+ // https://documentation-service.arm.com/static/5fce431be167456a35b36ade
+ //
+ // "Neighboring load and store single instructions can pipeline their address
+ // and data phases but in some cases, such as 32- bit opcodes aligned on odd
+ // halfword boundaries, they might not pipeline optimally."
if (MCID.getSize() == 4 && (MI->mayLoad() || MI->mayStore()))
return HazardType::NoopHazard;
>From 44fa8c14e67e1905a88eec27d04a9903c193922c Mon Sep 17 00:00:00 2001
From: Jon Roelofs <jonathan_roelofs at apple.com>
Date: Thu, 13 Feb 2025 11:29:29 -0800
Subject: [PATCH 06/11] move minsize check out of getHazardTypeAssumingOffset
---
llvm/lib/Target/ARM/ARMHazardRecognizer.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
index 51c8e02f1f1e1..fc523b31ddf7b 100644
--- a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
+++ b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
@@ -338,10 +338,6 @@ ARMCortexM4AlignmentHazardRecognizer::getHazardTypeAssumingOffset(
return HazardType::NoHazard;
}
- const Function &F = MI->getParent()->getParent()->getFunction();
- if (F.hasMinSize())
- return HazardType::NoHazard;
-
if (AssumedOffset % 4 == 0)
return HazardType::NoHazard;
@@ -395,6 +391,10 @@ unsigned ARMCortexM4AlignmentHazardRecognizer::PreEmitNoops(SUnit *SU) {
unsigned ARMCortexM4AlignmentHazardRecognizer::PreEmitNoops(MachineInstr *MI) {
const MachineBasicBlock *Parent = MI->getParent();
+ const Function &F = Parent->getParent()->getFunction();
+ if (F.hasMinSize())
+ return 0;
+
if (Parent != MBB) {
Offset = 0;
MBB = Parent;
>From 521a7986527790edb54a11899f80566620c1ec5b Mon Sep 17 00:00:00 2001
From: Jon Roelofs <jonathan_roelofs at apple.com>
Date: Thu, 13 Feb 2025 12:59:50 -0800
Subject: [PATCH 07/11] eol newline
---
llvm/lib/Target/ARM/ARMHazardRecognizer.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
index fc523b31ddf7b..aeebc28615314 100644
--- a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
+++ b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
@@ -440,4 +440,4 @@ ARMCortexM4AlignmentHazardRecognizer::getLoopFor(MachineInstr *MI) {
new (&MLI) MachineLoopInfo(MDT);
}
return MLI.getLoopFor(MI->getParent());
-}
\ No newline at end of file
+}
>From b8dfd88821cc7e04ce75891698b34449f5389cc1 Mon Sep 17 00:00:00 2001
From: Jon Roelofs <jonathan_roelofs at apple.com>
Date: Thu, 13 Feb 2025 13:56:24 -0800
Subject: [PATCH 08/11] make the test more concise, test ld/st path
---
.../ARM/cortex-m4f-alignment-hazard.mir | 276 +++++++-----------
1 file changed, 105 insertions(+), 171 deletions(-)
diff --git a/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir b/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir
index ed0bc0b755b97..b2765b30dc02d 100644
--- a/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir
+++ b/llvm/test/CodeGen/ARM/cortex-m4f-alignment-hazard.mir
@@ -3,6 +3,11 @@
# RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s -cortex-m4-alignment-hazard-rec-innermost-loops-only=0 | FileCheck %s --check-prefix=ANY-LOOPS
# RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s -cortex-m4-alignment-hazard-rec-loops-only=0 | FileCheck %s --check-prefix=ANY-BLOCK
--- |
+ define void @hazard_kinds() {
+ entry:
+ ret void
+ }
+
define void @alignment_hazards_in_double_loop() {
entry:
ret void
@@ -23,6 +28,106 @@
...
---
+name: hazard_kinds
+alignment: 4
+body: |
+ ; DEFAULT-LABEL: name: hazard_kinds
+ ; DEFAULT: bb.0 (align 4):
+ ; DEFAULT-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; DEFAULT-NEXT: {{ $}}
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: tHINT 0, 14 /* CC::al */, 0
+ ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: tHINT 0, 14 /* CC::al */, 0
+ ; DEFAULT-NEXT: $r1 = t2LDRi12 $r1, 0, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: tHINT 0, 14 /* CC::al */, 0
+ ; DEFAULT-NEXT: t2STRDi8 $r4, $r4, $r0, 192, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; DEFAULT-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; DEFAULT-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
+ ; DEFAULT-NEXT: {{ $}}
+ ; DEFAULT-NEXT: bb.1:
+ ; DEFAULT-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc
+ ;
+ ; ANY-LOOPS-LABEL: name: hazard_kinds
+ ; ANY-LOOPS: bb.0 (align 4):
+ ; ANY-LOOPS-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; ANY-LOOPS-NEXT: {{ $}}
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: tHINT 0, 14 /* CC::al */, 0
+ ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: tHINT 0, 14 /* CC::al */, 0
+ ; ANY-LOOPS-NEXT: $r1 = t2LDRi12 $r1, 0, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: tHINT 0, 14 /* CC::al */, 0
+ ; ANY-LOOPS-NEXT: t2STRDi8 $r4, $r4, $r0, 192, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; ANY-LOOPS-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; ANY-LOOPS-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
+ ; ANY-LOOPS-NEXT: {{ $}}
+ ; ANY-LOOPS-NEXT: bb.1:
+ ; ANY-LOOPS-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc
+ ;
+ ; ANY-BLOCK-LABEL: name: hazard_kinds
+ ; ANY-BLOCK: bb.0 (align 4):
+ ; ANY-BLOCK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; ANY-BLOCK-NEXT: {{ $}}
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
+ ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
+ ; ANY-BLOCK-NEXT: $r1 = t2LDRi12 $r1, 0, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
+ ; ANY-BLOCK-NEXT: t2STRDi8 $r4, $r4, $r0, 192, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; ANY-BLOCK-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; ANY-BLOCK-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
+ ; ANY-BLOCK-NEXT: {{ $}}
+ ; ANY-BLOCK-NEXT: bb.1:
+ ; ANY-BLOCK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc
+ bb.0 (align 4):
+ successors: %bb.0, %bb.1
+
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ $s2 = VMOVSR $r1, 14, $noreg
+
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ $s2 = VMOVSR $r1, 14, $noreg
+ renamable $s6 = VLDRS renamable $r3, 6, 14, $noreg
+
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ $r1 = t2LDRi12 $r1, 0, 14, $noreg
+
+ renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
+ t2STRDi8 $r4, $r4, $r0, 192, 14, $noreg
+
+ renamable $s2 = VLDRS renamable $r3, 4, 14, $noreg
+ renamable $r2 = t2LSRri renamable $lr, 1, 14, $noreg, $noreg
+
+ tBcc %bb.0, 1, killed $cpsr
+
+ bb.1:
+ tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc
+...
+---
name: alignment_hazards_in_double_loop
alignment: 4
body: |
@@ -33,46 +138,21 @@ body: |
; DEFAULT-NEXT: bb.1 (align 4):
; DEFAULT-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; DEFAULT-NEXT: {{ $}}
- ; DEFAULT-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; DEFAULT-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; DEFAULT-NEXT: tHINT 0, 14 /* CC::al */, 0
; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: tHINT 0, 14 /* CC::al */, 0
- ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
; DEFAULT-NEXT: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
; DEFAULT-NEXT: {{ $}}
; DEFAULT-NEXT: bb.2 (align 4):
; DEFAULT-NEXT: successors: %bb.0(0x40000000), %bb.3(0x40000000)
; DEFAULT-NEXT: {{ $}}
- ; DEFAULT-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; DEFAULT-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
; DEFAULT-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
; DEFAULT-NEXT: {{ $}}
; DEFAULT-NEXT: bb.3:
- ; DEFAULT-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; DEFAULT-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
; DEFAULT-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc
;
; ANY-LOOPS-LABEL: name: alignment_hazards_in_double_loop
@@ -82,48 +162,22 @@ body: |
; ANY-LOOPS-NEXT: bb.1 (align 4):
; ANY-LOOPS-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; ANY-LOOPS-NEXT: {{ $}}
- ; ANY-LOOPS-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; ANY-LOOPS-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: tHINT 0, 14 /* CC::al */, 0
; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: tHINT 0, 14 /* CC::al */, 0
- ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
; ANY-LOOPS-NEXT: {{ $}}
; ANY-LOOPS-NEXT: bb.2 (align 4):
; ANY-LOOPS-NEXT: successors: %bb.0(0x40000000), %bb.3(0x40000000)
; ANY-LOOPS-NEXT: {{ $}}
- ; ANY-LOOPS-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; ANY-LOOPS-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: tHINT 0, 14 /* CC::al */, 0
; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: tHINT 0, 14 /* CC::al */, 0
- ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
; ANY-LOOPS-NEXT: {{ $}}
; ANY-LOOPS-NEXT: bb.3:
- ; ANY-LOOPS-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; ANY-LOOPS-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc
;
; ANY-BLOCK-LABEL: name: alignment_hazards_in_double_loop
@@ -133,95 +187,42 @@ body: |
; ANY-BLOCK-NEXT: bb.1 (align 4):
; ANY-BLOCK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; ANY-BLOCK-NEXT: {{ $}}
- ; ANY-BLOCK-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; ANY-BLOCK-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
- ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
; ANY-BLOCK-NEXT: {{ $}}
; ANY-BLOCK-NEXT: bb.2 (align 4):
; ANY-BLOCK-NEXT: successors: %bb.0(0x40000000), %bb.3(0x40000000)
; ANY-BLOCK-NEXT: {{ $}}
- ; ANY-BLOCK-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; ANY-BLOCK-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
- ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
; ANY-BLOCK-NEXT: {{ $}}
; ANY-BLOCK-NEXT: bb.3:
- ; ANY-BLOCK-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; ANY-BLOCK-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
- ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc
bb.0 (align 4):
successors: %bb.1
bb.1 (align 4):
successors: %bb.1, %bb.2
-
- renamable $s2 = VLDRS renamable $r3, 4, 14, $noreg
- renamable $r2 = t2LSRri renamable $lr, 1, 14, $noreg, $noreg
renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14, $noreg
$s2 = VMOVSR $r1, 14, $noreg
- renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
- $s2 = VMOVSR $r1, 14, $noreg
- renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
- renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
- $s2 = VMOVSR $r1, 14, $noreg
- renamable $s6 = VLDRS renamable $r3, 6, 14, $noreg
tBcc %bb.1, 1, killed $cpsr
bb.2 (align 4):
successors: %bb.0, %bb.3
-
- renamable $s2 = VLDRS renamable $r3, 4, 14, $noreg
- renamable $r2 = t2LSRri renamable $lr, 1, 14, $noreg, $noreg
renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14, $noreg
$s2 = VMOVSR $r1, 14, $noreg
- renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
- $s2 = VMOVSR $r1, 14, $noreg
- renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
- renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
- $s2 = VMOVSR $r1, 14, $noreg
- renamable $s6 = VLDRS renamable $r3, 6, 14, $noreg
tBcc %bb.0, 1, killed $cpsr
bb.3:
- renamable $s2 = VLDRS renamable $r3, 4, 14, $noreg
- renamable $r2 = t2LSRri renamable $lr, 1, 14, $noreg, $noreg
renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14, $noreg
$s2 = VMOVSR $r1, 14, $noreg
- renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
- $s2 = VMOVSR $r1, 14, $noreg
- renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
- renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
- $s2 = VMOVSR $r1, 14, $noreg
- renamable $s6 = VLDRS renamable $r3, 6, 14, $noreg
tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc
...
---
@@ -232,16 +233,8 @@ body: |
; DEFAULT: bb.0 (align 4):
; DEFAULT-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; DEFAULT-NEXT: {{ $}}
- ; DEFAULT-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; DEFAULT-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
; DEFAULT-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
; DEFAULT-NEXT: {{ $}}
; DEFAULT-NEXT: bb.1:
@@ -251,16 +244,8 @@ body: |
; ANY-LOOPS: bb.0 (align 4):
; ANY-LOOPS-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; ANY-LOOPS-NEXT: {{ $}}
- ; ANY-LOOPS-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; ANY-LOOPS-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
; ANY-LOOPS-NEXT: {{ $}}
; ANY-LOOPS-NEXT: bb.1:
@@ -270,16 +255,8 @@ body: |
; ANY-BLOCK: bb.0 (align 4):
; ANY-BLOCK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; ANY-BLOCK-NEXT: {{ $}}
- ; ANY-BLOCK-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; ANY-BLOCK-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
; ANY-BLOCK-NEXT: {{ $}}
; ANY-BLOCK-NEXT: bb.1:
@@ -287,16 +264,8 @@ body: |
bb.0 (align 4):
successors: %bb.0, %bb.1
- renamable $s2 = VLDRS renamable $r3, 4, 14, $noreg
- renamable $r2 = t2LSRri renamable $lr, 1, 14, $noreg, $noreg
renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14, $noreg
$s2 = VMOVSR $r1, 14, $noreg
- renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
- $s2 = VMOVSR $r1, 14, $noreg
- renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
- renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
- $s2 = VMOVSR $r1, 14, $noreg
- renamable $s6 = VLDRS renamable $r3, 6, 14, $noreg
tBcc %bb.0, 1, killed $cpsr
bb.1:
@@ -310,18 +279,9 @@ body: |
; DEFAULT: bb.0 (align 4):
; DEFAULT-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; DEFAULT-NEXT: {{ $}}
- ; DEFAULT-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; DEFAULT-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; DEFAULT-NEXT: tHINT 0, 14 /* CC::al */, 0
; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: tHINT 0, 14 /* CC::al */, 0
- ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; DEFAULT-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
; DEFAULT-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
; DEFAULT-NEXT: {{ $}}
; DEFAULT-NEXT: bb.1:
@@ -331,18 +291,9 @@ body: |
; ANY-LOOPS: bb.0 (align 4):
; ANY-LOOPS-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; ANY-LOOPS-NEXT: {{ $}}
- ; ANY-LOOPS-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; ANY-LOOPS-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: tHINT 0, 14 /* CC::al */, 0
; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: tHINT 0, 14 /* CC::al */, 0
- ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-LOOPS-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
; ANY-LOOPS-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
; ANY-LOOPS-NEXT: {{ $}}
; ANY-LOOPS-NEXT: bb.1:
@@ -352,18 +303,9 @@ body: |
; ANY-BLOCK: bb.0 (align 4):
; ANY-BLOCK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; ANY-BLOCK-NEXT: {{ $}}
- ; ANY-BLOCK-NEXT: renamable $s2 = VLDRS renamable $r3, 4, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; ANY-BLOCK-NEXT: renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: tHINT 0, 14 /* CC::al */, 0
- ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; ANY-BLOCK-NEXT: renamable $s6 = VLDRS renamable $r3, 6, 14 /* CC::al */, $noreg
; ANY-BLOCK-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
; ANY-BLOCK-NEXT: {{ $}}
; ANY-BLOCK-NEXT: bb.1:
@@ -371,16 +313,8 @@ body: |
bb.0 (align 4):
successors: %bb.0, %bb.1
- renamable $s2 = VLDRS renamable $r3, 4, 14, $noreg
- renamable $r2 = t2LSRri renamable $lr, 1, 14, $noreg, $noreg
renamable $r1, dead $cpsr = tLSRri renamable $r2, 1, 14, $noreg
$s2 = VMOVSR $r1, 14, $noreg
- renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
- $s2 = VMOVSR $r1, 14, $noreg
- renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
- renamable $r2, dead $cpsr = tLSRri renamable $r1, 1, 14, $noreg
- $s2 = VMOVSR $r1, 14, $noreg
- renamable $s6 = VLDRS renamable $r3, 6, 14, $noreg
tBcc %bb.0, 1, killed $cpsr
bb.1:
>From b40a2a4f516087dbd9ab07fa65a996aa80b7e942 Mon Sep 17 00:00:00 2001
From: Jon Roelofs <jonathan_roelofs at apple.com>
Date: Sun, 16 Feb 2025 10:36:21 -0800
Subject: [PATCH 09/11] move it under a target feature
---
llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 4 ++--
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 12 +++++-----
llvm/lib/Target/ARM/ARMFeatures.td | 6 +++++
llvm/lib/Target/ARM/ARMHazardRecognizer.cpp | 26 ++++++++++-----------
llvm/lib/Target/ARM/ARMHazardRecognizer.h | 4 ++--
llvm/lib/Target/ARM/ARMInstrInfo.h | 2 +-
llvm/lib/Target/ARM/ARMProcessors.td | 3 ++-
llvm/lib/Target/ARM/ARMSubtarget.h | 1 -
8 files changed, 32 insertions(+), 26 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index 83d6b365605b6..b8572cf1e1468 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -1447,8 +1447,8 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
}
if (MI->getAsmPrinterFlag(
- MachineInstr::CommentFlag(ARM::M4F_ALIGNMENT_HAZARD)))
- OutStreamer->AddComment("cortex-m4f alignment hazard");
+ MachineInstr::CommentFlag(ARM::ALIGNMENT_HAZARD)))
+ OutStreamer->AddComment("alignment hazard");
// Emit unwinding stuff for frame-related instructions
if (Subtarget->isTargetEHABICompatible() &&
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index ed0044b6e311d..dc2ba87aa09d6 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -151,9 +151,9 @@ ScheduleHazardRecognizer *ARMBaseInstrInfo::CreateTargetMIHazardRecognizer(
MHR->AddHazardRecognizer(
std::make_unique<ARMBankConflictHazardRecognizer>(DAG, 0x4, true));
- if (Subtarget.isCortexM4() && !DAG->hasVRegLiveness())
+ if (Subtarget.hasCortexM4FAlignmentHazards() && !DAG->hasVRegLiveness())
MHR->AddHazardRecognizer(
- std::make_unique<ARMCortexM4AlignmentHazardRecognizer>(
+ std::make_unique<ARMCortexM4FAlignmentHazardRecognizer>(
DAG->MF.getSubtarget()));
// Not inserting ARMHazardRecognizerFPMLx because that would change
@@ -173,9 +173,9 @@ CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
if (Subtarget.isThumb2() || Subtarget.hasVFP2Base())
MHR->AddHazardRecognizer(std::make_unique<ARMHazardRecognizerFPMLx>());
- if (Subtarget.isCortexM4())
+ if (Subtarget.hasCortexM4FAlignmentHazards())
MHR->AddHazardRecognizer(
- std::make_unique<ARMCortexM4AlignmentHazardRecognizer>(
+ std::make_unique<ARMCortexM4FAlignmentHazardRecognizer>(
DAG->MF.getSubtarget()));
auto BHR = TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
@@ -186,10 +186,10 @@ CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
ScheduleHazardRecognizer *ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer(
const MachineFunction &MF) const {
- if (!Subtarget.isCortexM4())
+ if (!Subtarget.hasCortexM4FAlignmentHazards())
return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(MF);
- return new ARMCortexM4AlignmentHazardRecognizer(MF.getSubtarget());
+ return new ARMCortexM4FAlignmentHazardRecognizer(MF.getSubtarget());
}
MachineInstr *
diff --git a/llvm/lib/Target/ARM/ARMFeatures.td b/llvm/lib/Target/ARM/ARMFeatures.td
index bb437698296ce..a5df83488b160 100644
--- a/llvm/lib/Target/ARM/ARMFeatures.td
+++ b/llvm/lib/Target/ARM/ARMFeatures.td
@@ -316,6 +316,12 @@ def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx",
def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
"true", "Has VMLx hazards">;
+// Cortex-M4 has an alignment hazard in its prefetcher that inserts a bubble
+// during some sequences of odd-halfword aligned 32 bit instructions.
+// https://developer.arm.com/documentation/ka006138/latest
+def FeatureHasCortexM4FAlignmentHazards : SubtargetFeature<"m4f-hazards",
+ "HasCortexM4FAlignmentHazards", "true", "Has Cortex-m4f alignment hazards">;
+
// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
// VFP to NEON, as an execution domain optimization.
// True if VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
diff --git a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
index aeebc28615314..ca830cf0c15a1 100644
--- a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
+++ b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
@@ -285,16 +285,16 @@ static cl::opt<bool>
cl::init(true),
cl::desc("Emit noops only in innermost loops"));
-void ARMCortexM4AlignmentHazardRecognizer::Reset() { Offset = 0; }
+void ARMCortexM4FAlignmentHazardRecognizer::Reset() { Offset = 0; }
-ARMCortexM4AlignmentHazardRecognizer::ARMCortexM4AlignmentHazardRecognizer(
+ARMCortexM4FAlignmentHazardRecognizer::ARMCortexM4FAlignmentHazardRecognizer(
const MCSubtargetInfo &STI)
: STI(STI), MBB(nullptr), MF(nullptr), Offset(0), Advanced(false),
EmittingNoop(false) {
MaxLookAhead = 1;
}
-void ARMCortexM4AlignmentHazardRecognizer::EmitInstruction(SUnit *SU) {
+void ARMCortexM4FAlignmentHazardRecognizer::EmitInstruction(SUnit *SU) {
if (!SU->isInstr())
return;
@@ -303,7 +303,7 @@ void ARMCortexM4AlignmentHazardRecognizer::EmitInstruction(SUnit *SU) {
return EmitInstruction(MI);
}
-void ARMCortexM4AlignmentHazardRecognizer::EmitInstruction(MachineInstr *MI) {
+void ARMCortexM4FAlignmentHazardRecognizer::EmitInstruction(MachineInstr *MI) {
if (MI->isDebugInstr())
return;
@@ -314,13 +314,13 @@ void ARMCortexM4AlignmentHazardRecognizer::EmitInstruction(MachineInstr *MI) {
// it with an AsmPrinter comment.
if (EmittingNoop)
if (MachineInstr *Prev = MI->getPrevNode())
- Prev->setAsmPrinterFlag(ARM::M4F_ALIGNMENT_HAZARD);
+ Prev->setAsmPrinterFlag(ARM::ALIGNMENT_HAZARD);
EmittingNoop = false;
}
ScheduleHazardRecognizer::HazardType
-ARMCortexM4AlignmentHazardRecognizer::getHazardType(SUnit *SU,
+ARMCortexM4FAlignmentHazardRecognizer::getHazardType(SUnit *SU,
int /*Ignored*/) {
if (!SU->isInstr())
return HazardType::NoHazard;
@@ -331,7 +331,7 @@ ARMCortexM4AlignmentHazardRecognizer::getHazardType(SUnit *SU,
}
ScheduleHazardRecognizer::HazardType
-ARMCortexM4AlignmentHazardRecognizer::getHazardTypeAssumingOffset(
+ARMCortexM4FAlignmentHazardRecognizer::getHazardTypeAssumingOffset(
MachineInstr *MI, size_t AssumedOffset) {
if (Advanced) {
Advanced = false;
@@ -375,12 +375,12 @@ ARMCortexM4AlignmentHazardRecognizer::getHazardTypeAssumingOffset(
return HazardType::NoHazard;
}
-void ARMCortexM4AlignmentHazardRecognizer::AdvanceCycle() { Advanced = true; }
-void ARMCortexM4AlignmentHazardRecognizer::RecedeCycle() {}
+void ARMCortexM4FAlignmentHazardRecognizer::AdvanceCycle() { Advanced = true; }
+void ARMCortexM4FAlignmentHazardRecognizer::RecedeCycle() {}
-void ARMCortexM4AlignmentHazardRecognizer::EmitNoop() { Offset += 2; }
+void ARMCortexM4FAlignmentHazardRecognizer::EmitNoop() { Offset += 2; }
-unsigned ARMCortexM4AlignmentHazardRecognizer::PreEmitNoops(SUnit *SU) {
+unsigned ARMCortexM4FAlignmentHazardRecognizer::PreEmitNoops(SUnit *SU) {
if (!SU->isInstr())
return 0;
@@ -389,7 +389,7 @@ unsigned ARMCortexM4AlignmentHazardRecognizer::PreEmitNoops(SUnit *SU) {
return PreEmitNoops(MI);
}
-unsigned ARMCortexM4AlignmentHazardRecognizer::PreEmitNoops(MachineInstr *MI) {
+unsigned ARMCortexM4FAlignmentHazardRecognizer::PreEmitNoops(MachineInstr *MI) {
const MachineBasicBlock *Parent = MI->getParent();
const Function &F = Parent->getParent()->getFunction();
if (F.hasMinSize())
@@ -430,7 +430,7 @@ unsigned ARMCortexM4AlignmentHazardRecognizer::PreEmitNoops(MachineInstr *MI) {
}
const MachineLoop *
-ARMCortexM4AlignmentHazardRecognizer::getLoopFor(MachineInstr *MI) {
+ARMCortexM4FAlignmentHazardRecognizer::getLoopFor(MachineInstr *MI) {
// Calculate and cache the MachineLoopInfo.
MachineFunction *ParentMF = MI->getParent()->getParent();
if (MF != ParentMF) {
diff --git a/llvm/lib/Target/ARM/ARMHazardRecognizer.h b/llvm/lib/Target/ARM/ARMHazardRecognizer.h
index 5e2c4e7bef27a..3e8f976a7f800 100644
--- a/llvm/lib/Target/ARM/ARMHazardRecognizer.h
+++ b/llvm/lib/Target/ARM/ARMHazardRecognizer.h
@@ -74,7 +74,7 @@ class ARMBankConflictHazardRecognizer : public ScheduleHazardRecognizer {
odd halfword boundaries will experience a performance drop. Specifically, one
stall cycle is inserted for every three instructions executed."
*/
-class ARMCortexM4AlignmentHazardRecognizer : public ScheduleHazardRecognizer {
+class ARMCortexM4FAlignmentHazardRecognizer : public ScheduleHazardRecognizer {
const MCSubtargetInfo &STI;
const MachineBasicBlock *MBB;
MachineDominatorTree MDT;
@@ -85,7 +85,7 @@ class ARMCortexM4AlignmentHazardRecognizer : public ScheduleHazardRecognizer {
bool EmittingNoop;
public:
- ARMCortexM4AlignmentHazardRecognizer(const MCSubtargetInfo &STI);
+ ARMCortexM4FAlignmentHazardRecognizer(const MCSubtargetInfo &STI);
void Reset() override;
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.h b/llvm/lib/Target/ARM/ARMInstrInfo.h
index 6e988a1113583..8fab0890945c2 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.h
@@ -43,7 +43,7 @@ class ARMInstrInfo : public ARMBaseInstrInfo {
namespace ARM {
enum AsmComments {
- M4F_ALIGNMENT_HAZARD = MachineInstr::TAsmComments,
+ ALIGNMENT_HAZARD = MachineInstr::TAsmComments,
};
} // namespace ARM
}
diff --git a/llvm/lib/Target/ARM/ARMProcessors.td b/llvm/lib/Target/ARM/ARMProcessors.td
index 046a67c0c472d..104846d2446ac 100644
--- a/llvm/lib/Target/ARM/ARMProcessors.td
+++ b/llvm/lib/Target/ARM/ARMProcessors.td
@@ -348,7 +348,8 @@ def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em,
FeatureHasSlowFPVMLx,
FeatureHasSlowFPVFMx,
FeatureUseMISched,
- FeatureHasNoBranchPredictor]>;
+ FeatureHasNoBranchPredictor,
+ FeatureHasCortexM4FAlignmentHazards]>;
def : ProcessorModel<"cortex-m7", CortexM7Model, [ARMv7em,
ProcM7,
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index 86f3ca61418bf..7329d3f2055f0 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -292,7 +292,6 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
bool isSwift() const { return ARMProcFamily == Swift; }
bool isCortexM3() const { return ARMProcFamily == CortexM3; }
bool isCortexM55() const { return ARMProcFamily == CortexM55; }
- bool isCortexM4() const { return ARMProcFamily == CortexM4; }
bool isCortexM7() const { return ARMProcFamily == CortexM7; }
bool isCortexM85() const { return ARMProcFamily == CortexM85; }
bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
>From 36b1ff08734dda441835410b26d3c0a3837b5c79 Mon Sep 17 00:00:00 2001
From: Jon Roelofs <jonathan_roelofs at apple.com>
Date: Sun, 16 Feb 2025 10:42:56 -0800
Subject: [PATCH 10/11] move new pass before layout-picky passes
---
llvm/lib/Target/ARM/ARMTargetMachine.cpp | 11 +++++------
llvm/test/CodeGen/ARM/O3-pipeline.ll | 2 +-
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index a988c2e3269fa..da46d6fc7f5e8 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -608,6 +608,11 @@ void ARMPassConfig::addPreEmitPass2() {
// be inserted at the start of blocks and at within blocks so this pass has to
// come before those below.
addPass(createARMFixCortexA57AES1742098Pass());
+ // Enable the hazard recognizer for cortex-m4f at -O2 or higher.
+ if ((EnablePostRAHazardRecognizer == cl::BOU_UNSET &&
+ CodeGenOptLevel::Default <= getOptLevel()) ||
+ EnablePostRAHazardRecognizer == cl::BOU_TRUE)
+ addPass(&PostRAHazardRecognizerID);
// Inserts BTIs at the start of functions and indirectly-called basic blocks,
// so passes cannot add to the start of basic blocks once this has run.
addPass(createARMBranchTargetsPass());
@@ -626,12 +631,6 @@ void ARMPassConfig::addPreEmitPass2() {
// Identify valid eh continuation targets for Windows EHCont Guard.
addPass(createEHContGuardCatchretPass());
}
-
- // Enable the hazard recognizer for cortex-m4f at -O2 or higher.
- if ((EnablePostRAHazardRecognizer == cl::BOU_UNSET &&
- CodeGenOptLevel::Default <= getOptLevel()) ||
- EnablePostRAHazardRecognizer == cl::BOU_TRUE)
- addPass(&PostRAHazardRecognizerID);
}
yaml::MachineFunctionInfo *
diff --git a/llvm/test/CodeGen/ARM/O3-pipeline.ll b/llvm/test/CodeGen/ARM/O3-pipeline.ll
index a3930c349b5d4..a642f8c147df6 100644
--- a/llvm/test/CodeGen/ARM/O3-pipeline.ll
+++ b/llvm/test/CodeGen/ARM/O3-pipeline.ll
@@ -206,6 +206,7 @@
; CHECK-NEXT: Stack Frame Layout Analysis
; CHECK-NEXT: ReachingDefAnalysis
; CHECK-NEXT: ARM fix for Cortex-A57 AES Erratum 1742098
+; CHECK-NEXT: Post RA hazard recognizer
; CHECK-NEXT: ARM Branch Targets
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: ARM constant island placement and branch shortening pass
@@ -213,7 +214,6 @@
; CHECK-NEXT: Machine Natural Loop Construction
; CHECK-NEXT: ReachingDefAnalysis
; CHECK-NEXT: ARM Low Overhead Loops pass
-; CHECK-NEXT: Post RA hazard recognizer
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: ARM Assembly Printer
>From 11cdfacb059a3d88d71c7f5ad61b9ee1bab7cad5 Mon Sep 17 00:00:00 2001
From: Jon Roelofs <jonathan_roelofs at apple.com>
Date: Sun, 16 Feb 2025 10:45:18 -0800
Subject: [PATCH 11/11] remove ProcM4; no longer need it
---
llvm/lib/Target/ARM/ARMProcessors.td | 3 ---
llvm/lib/Target/ARM/ARMSubtarget.cpp | 1 -
2 files changed, 4 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMProcessors.td b/llvm/lib/Target/ARM/ARMProcessors.td
index 104846d2446ac..89b29361b3ca7 100644
--- a/llvm/lib/Target/ARM/ARMProcessors.td
+++ b/llvm/lib/Target/ARM/ARMProcessors.td
@@ -99,8 +99,6 @@ def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
"Cortex-M3 ARM processors", []>;
def ProcM55 : SubtargetFeature<"m55", "ARMProcFamily", "CortexM55",
"Cortex-M55 ARM processors", []>;
-def ProcM4 : SubtargetFeature<"m4", "ARMProcFamily", "CortexM4",
- "Cortex-M4 ARM processors", []>;
def ProcM7 : SubtargetFeature<"m7", "ARMProcFamily", "CortexM7",
"Cortex-M7 ARM processors", []>;
def ProcM85 : SubtargetFeature<"m85", "ARMProcFamily", "CortexM85",
@@ -342,7 +340,6 @@ def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m,
FeatureHasNoBranchPredictor]>;
def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em,
- ProcM4,
FeatureVFP4_D16_SP,
FeaturePreferBranchAlign32,
FeatureHasSlowFPVMLx,
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index a1fbb387cce09..893084785e6f0 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -289,7 +289,6 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
case CortexA78C:
case CortexA510:
case CortexA710:
- case CortexM4:
case CortexR4:
case CortexR5:
case CortexR7:
More information about the llvm-commits
mailing list