[llvm] [Hexagon] Explicitly truncate constant in UAddSubO (PR #127360)

[Brian Cain via llvm-commits]

https://github.com/androm3da updated https://github.com/llvm/llvm-project/pull/127360

>From 9d11ba7e836b8c88ca0cf2e1a0941a57c1395556 Mon Sep 17 00:00:00 2001
From: Brian Cain <bcain at quicinc.com>
Date: Sat, 15 Feb 2025 18:49:25 -0600
Subject: [PATCH] [Hexagon] Explicitly truncate constant in UAddSubO

After #117558 landed, this code would assert "Value is not an N-bit unsigned
value" in getConstant(), from a test case in zig.

Co-authored-by:  Craig Topper <craig.topper at sifive.com>
Fixes #127296
---
 .../lib/Target/Hexagon/HexagonISelLowering.cpp |  2 +-
 llvm/test/CodeGen/Hexagon/iss127296.ll         | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/Hexagon/iss127296.ll

diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 1a7667fe42fbc..b31360b4096da 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -3273,7 +3273,7 @@ HexagonTargetLowering::LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const {
     if (Opc == ISD::USUBO) {
       SDValue Op = DAG.getNode(ISD::SUB, dl, VTs.VTs[0], {X, Y});
       SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op,
-                                DAG.getConstant(-1, dl, ty(Op)), ISD::SETEQ);
+                                DAG.getAllOnesConstant(dl, ty(Op)), ISD::SETEQ);
       return DAG.getMergeValues({Op, Ov}, dl);
     }
   }
diff --git a/llvm/test/CodeGen/Hexagon/iss127296.ll b/llvm/test/CodeGen/Hexagon/iss127296.ll
new file mode 100644
index 0000000000000..bf0e7a9881014
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/iss127296.ll
@@ -0,0 +1,18 @@
+; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s
+
+; CHECK: r0 = add(r0,#-1)
+
+define fastcc void @os.linux.tls.initStatic(i32 %x) {
+  %1 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %x, i32 1)
+  br label %2
+
+  2:                                                ; preds = %0
+  %3 = extractvalue { i32, i1 } %1, 0
+  ret void
+}
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #0
+
+attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+