[llvm] [PowerPC] $carry should be added to successors liveins if still alive (PR #127376)
Kai Luo via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 15 21:48:17 PST 2025
https://github.com/bzEq updated https://github.com/llvm/llvm-project/pull/127376
>From abd4882768b2796f5a3a20e887ae542644eccbd9 Mon Sep 17 00:00:00 2001
From: Kai Luo <gluokai at gmail.com>
Date: Sun, 16 Feb 2025 13:42:42 +0800
Subject: [PATCH 1/2] [PowerPC] $carry should be added to successors liveins if
still alive
Fix bug reported in https://github.com/llvm/llvm-project/pull/116984.
The fix is similar to 647e861e080382593648b234668ad2f5a376ac5e.
---
llvm/include/llvm/CodeGen/LivePhysRegs.h | 3 +
llvm/lib/CodeGen/LivePhysRegs.cpp | 22 +++++
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 5 ++
llvm/lib/Target/X86/X86ISelLowering.cpp | 18 +---
.../carry-liveness-after-expand-isel.ll | 83 +++++++++++++++++++
5 files changed, 115 insertions(+), 16 deletions(-)
create mode 100644 llvm/test/CodeGen/PowerPC/carry-liveness-after-expand-isel.ll
diff --git a/llvm/include/llvm/CodeGen/LivePhysRegs.h b/llvm/include/llvm/CodeGen/LivePhysRegs.h
index 037905119eb22..596e2b76aabb6 100644
--- a/llvm/include/llvm/CodeGen/LivePhysRegs.h
+++ b/llvm/include/llvm/CodeGen/LivePhysRegs.h
@@ -195,6 +195,9 @@ void addLiveIns(MachineBasicBlock &MBB, const LivePhysRegs &LiveRegs);
void computeAndAddLiveIns(LivePhysRegs &LiveRegs,
MachineBasicBlock &MBB);
+/// Check if physical register \p Reg is alive after \p MBI.
+bool isPhysRegLiveAfter(Register Reg, MachineBasicBlock::iterator MBI);
+
/// Convenience function for recomputing live-in's for a MBB. Returns true if
/// any changes were made.
static inline bool recomputeLiveIns(MachineBasicBlock &MBB) {
diff --git a/llvm/lib/CodeGen/LivePhysRegs.cpp b/llvm/lib/CodeGen/LivePhysRegs.cpp
index 2ba17e46be5a6..e50789d63d5d9 100644
--- a/llvm/lib/CodeGen/LivePhysRegs.cpp
+++ b/llvm/lib/CodeGen/LivePhysRegs.cpp
@@ -338,3 +338,25 @@ void llvm::computeAndAddLiveIns(LivePhysRegs &LiveRegs,
computeLiveIns(LiveRegs, MBB);
addLiveIns(MBB, LiveRegs);
}
+
+bool llvm::isPhysRegLiveAfter(Register Reg, MachineBasicBlock::iterator MBI) {
+ assert(Reg.isPhysical() && "Apply to physical register only");
+
+ MachineBasicBlock *MBB = MBI->getParent();
+ // Scan forward through BB for a use/def of Reg .
+ for (const MachineInstr &MI : llvm::make_range(std::next(MBI), MBB->end())) {
+ if (MI.readsRegister(Reg, /*TRI=*/nullptr))
+ return true;
+ // If we found a def, we can stop searching.
+ if (MI.definesRegister(Reg, /*TRI=*/nullptr))
+ return false;
+ }
+
+ // If we hit the end of the block, check whether Reg is live into a
+ // successor.
+ for (MachineBasicBlock *Succ : MBB->successors())
+ if (Succ->isLiveIn(Reg))
+ return true;
+
+ return false;
+}
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index f1195feea80e8..c3baac2aa30be 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -36,6 +36,7 @@
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/ISDOpcodes.h"
+#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
@@ -13296,6 +13297,10 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
DebugLoc dl = MI.getDebugLoc();
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
+ if (isPhysRegLiveAfter(PPC::CARRY , MI.getIterator())) {
+ copy0MBB->addLiveIn(PPC::CARRY);
+ sinkMBB->addLiveIn(PPC::CARRY);
+ }
// Set the call frame size on entry to the new basic blocks.
// See https://reviews.llvm.org/D156113.
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 9592137b34842..86b7a333ccc12 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -28,6 +28,7 @@
#include "llvm/Analysis/ProfileSummaryInfo.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/IntrinsicLowering.h"
+#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -35349,22 +35350,7 @@ MVT X86TargetLowering::getPreferredSwitchConditionType(LLVMContext &Context,
// basic block or any successors of the basic block.
static bool isEFLAGSLiveAfter(MachineBasicBlock::iterator Itr,
MachineBasicBlock *BB) {
- // Scan forward through BB for a use/def of EFLAGS.
- for (const MachineInstr &mi : llvm::make_range(std::next(Itr), BB->end())) {
- if (mi.readsRegister(X86::EFLAGS, /*TRI=*/nullptr))
- return true;
- // If we found a def, we can stop searching.
- if (mi.definesRegister(X86::EFLAGS, /*TRI=*/nullptr))
- return false;
- }
-
- // If we hit the end of the block, check whether EFLAGS is live into a
- // successor.
- for (MachineBasicBlock *Succ : BB->successors())
- if (Succ->isLiveIn(X86::EFLAGS))
- return true;
-
- return false;
+ return isPhysRegLiveAfter(X86::EFLAGS, Itr);
}
/// Utility function to emit xbegin specifying the start of an RTM region.
diff --git a/llvm/test/CodeGen/PowerPC/carry-liveness-after-expand-isel.ll b/llvm/test/CodeGen/PowerPC/carry-liveness-after-expand-isel.ll
new file mode 100644
index 0000000000000..7cf326041c5ec
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/carry-liveness-after-expand-isel.ll
@@ -0,0 +1,83 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck %s
+
+target datalayout = "E-m:e-p:32:32-Fn32-i64:64-n32"
+target triple = "powerpc-unknown-linux-gnu"
+
+ at md_seq_show___trans_tmp_57 = external global i8
+
+define i32 @md_seq_show(i64 %0, i32 %1) #0 {
+ ; CHECK-LABEL: name: md_seq_show
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
+ ; CHECK-NEXT: liveins: $r3, $r4, $r5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprc = COPY $r5
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY $r4
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprc = COPY $r3
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprc = COPY [[COPY1]]
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gprc = COPY [[COPY2]]
+ ; CHECK-NEXT: [[ADDIC:%[0-9]+]]:gprc = ADDIC [[COPY1]], 1, implicit-def $carry
+ ; CHECK-NEXT: [[CMPLWI:%[0-9]+]]:crrc = CMPLWI killed [[ADDIC]], 1
+ ; CHECK-NEXT: [[LI:%[0-9]+]]:gprc_and_gprc_nor0 = LI 0
+ ; CHECK-NEXT: [[LI1:%[0-9]+]]:gprc_and_gprc_nor0 = LI 1
+ ; CHECK-NEXT: BCC 44, [[CMPLWI]], %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.entry:
+ ; CHECK-NEXT: successors: %bb.4(0x80000000)
+ ; CHECK-NEXT: liveins: $carry
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.entry:
+ ; CHECK-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000)
+ ; CHECK-NEXT: liveins: $carry
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gprc_and_gprc_nor0 = PHI [[LI]], %bb.3, [[LI1]], %bb.0
+ ; CHECK-NEXT: [[ADDZE:%[0-9]+]]:gprc = ADDZE [[COPY2]], implicit-def dead $carry, implicit $carry
+ ; CHECK-NEXT: [[ADDIC1:%[0-9]+]]:gprc = ADDIC [[ADDZE]], -1, implicit-def $carry
+ ; CHECK-NEXT: [[SUBFE:%[0-9]+]]:gprc_and_gprc_nor0 = SUBFE killed [[ADDIC1]], [[ADDZE]], implicit-def dead $carry, implicit $carry
+ ; CHECK-NEXT: [[CMPLWI1:%[0-9]+]]:crrc = CMPLWI [[ADDZE]], 0
+ ; CHECK-NEXT: BCC 76, [[CMPLWI1]], %bb.6
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.entry:
+ ; CHECK-NEXT: successors: %bb.6(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.entry:
+ ; CHECK-NEXT: successors: %bb.1(0x55555556), %bb.2(0x2aaaaaaa)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gprc = PHI [[SUBFE]], %bb.5, [[PHI]], %bb.4
+ ; CHECK-NEXT: [[CMPLWI2:%[0-9]+]]:crrc = CMPLWI killed [[PHI1]], 0
+ ; CHECK-NEXT: BCC 68, killed [[CMPLWI2]], %bb.2
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.for.cond.i.preheader:
+ ; CHECK-NEXT: [[LI2:%[0-9]+]]:gprc = LI 0
+ ; CHECK-NEXT: $r3 = COPY [[LI2]]
+ ; CHECK-NEXT: BLR implicit $lr, implicit $rm, implicit $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.status_resync.exit:
+ ; CHECK-NEXT: [[ADDIC2:%[0-9]+]]:gprc = ADDIC [[COPY]], -1, implicit-def $carry
+ ; CHECK-NEXT: [[SUBFE1:%[0-9]+]]:gprc = SUBFE killed [[ADDIC2]], [[COPY]], implicit-def dead $carry, implicit $carry
+ ; CHECK-NEXT: [[LIS:%[0-9]+]]:gprc_and_gprc_nor0 = LIS target-flags(ppc-ha) @md_seq_show___trans_tmp_57
+ ; CHECK-NEXT: STB killed [[SUBFE1]], target-flags(ppc-lo) @md_seq_show___trans_tmp_57, killed [[LIS]] :: (store (s8) into @md_seq_show___trans_tmp_57)
+ ; CHECK-NEXT: [[LI3:%[0-9]+]]:gprc = LI 0
+ ; CHECK-NEXT: $r3 = COPY [[LI3]]
+ ; CHECK-NEXT: BLR implicit $lr, implicit $rm, implicit $r3
+entry:
+ switch i64 %0, label %status_resync.exit [
+ i64 -1, label %for.cond.i.preheader
+ i64 0, label %for.cond.i.preheader
+ ]
+
+for.cond.i.preheader: ; preds = %entry, %entry
+ ret i32 0
+
+status_resync.exit: ; preds = %entry
+ %tobool = icmp ne i32 %1, 0
+ %storedv = zext i1 %tobool to i8
+ store i8 %storedv, ptr @md_seq_show___trans_tmp_57, align 1
+ ret i32 0
+}
+
+attributes #0 = { "target-features"="-aix-shared-lib-tls-model-opt,-aix-small-local-dynamic-tls,-aix-small-local-exec-tls,-altivec,-bpermd,-crbits,-crypto,-direct-move,-extdiv,-htm,-isa-v206-instructions,-isa-v207-instructions,-isa-v30-instructions,-power8-vector,-power9-vector,-privileged,-quadword-atomics,-rop-protect,-spe,-vsx" }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
>From d556765b095edc873113c6431cabe0db717b7b42 Mon Sep 17 00:00:00 2001
From: Kai Luo <gluokai at gmail.com>
Date: Sun, 16 Feb 2025 13:48:04 +0800
Subject: [PATCH 2/2] Remove redundant lines
---
llvm/test/CodeGen/PowerPC/carry-liveness-after-expand-isel.ll | 2 --
1 file changed, 2 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/carry-liveness-after-expand-isel.ll b/llvm/test/CodeGen/PowerPC/carry-liveness-after-expand-isel.ll
index 7cf326041c5ec..d902972ae00ea 100644
--- a/llvm/test/CodeGen/PowerPC/carry-liveness-after-expand-isel.ll
+++ b/llvm/test/CodeGen/PowerPC/carry-liveness-after-expand-isel.ll
@@ -79,5 +79,3 @@ status_resync.exit: ; preds = %entry
}
attributes #0 = { "target-features"="-aix-shared-lib-tls-model-opt,-aix-small-local-dynamic-tls,-aix-small-local-exec-tls,-altivec,-bpermd,-crbits,-crypto,-direct-move,-extdiv,-htm,-isa-v206-instructions,-isa-v207-instructions,-isa-v30-instructions,-power8-vector,-power9-vector,-privileged,-quadword-atomics,-rop-protect,-spe,-vsx" }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK: {{.*}}
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