[llvm] bfdf30e - [AArch64] Add patterns for addv(sext) and addv(zext)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 15 09:04:37 PST 2025
Author: David Green
Date: 2025-02-15T17:04:32Z
New Revision: bfdf30e9b3d0b49344a651a5c7cd87be31d255c4
URL: https://github.com/llvm/llvm-project/commit/bfdf30e9b3d0b49344a651a5c7cd87be31d255c4
DIFF: https://github.com/llvm/llvm-project/commit/bfdf30e9b3d0b49344a651a5c7cd87be31d255c4.diff
LOG: [AArch64] Add patterns for addv(sext) and addv(zext)
This adds patterns for v8i8->i16 vaddlv and v4i16->i32 vaddlv, for both signed
and unsigned extends.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/test/CodeGen/AArch64/arm64-vabs.ll
llvm/test/CodeGen/AArch64/neon-dotreduce.ll
llvm/test/CodeGen/AArch64/vecreduce-add.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index c45b311b6ebb2..c9549f12769d1 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -7357,6 +7357,19 @@ defm FMAXV : SIMDFPAcrossLanes<0b01111, 0, "fmaxv", AArch64fmaxv>;
defm FMINNMV : SIMDFPAcrossLanes<0b01100, 1, "fminnmv", AArch64fminnmv>;
defm FMINV : SIMDFPAcrossLanes<0b01111, 1, "fminv", AArch64fminv>;
+def : Pat<(i32 (vector_extract (v8i16 (AArch64uaddv (v8i16 (sext (v8i8 V64:$op))))), (i64 0))),
+ (EXTRACT_SUBREG (v8i16 (SUBREG_TO_REG (i64 0), (SADDLVv8i8v V64:$op), hsub)), ssub)>;
+def : Pat<(i32 (vector_extract (v8i16 (AArch64uaddv (v8i16 (zext (v8i8 V64:$op))))), (i64 0))),
+ (EXTRACT_SUBREG (v8i16 (SUBREG_TO_REG (i64 0), (UADDLVv8i8v V64:$op), hsub)), ssub)>;
+def : Pat<(v8i16 (AArch64uaddv (v8i16 (sext (v8i8 V64:$op))))),
+ (v8i16 (SUBREG_TO_REG (i64 0), (SADDLVv8i8v V64:$op), hsub))>;
+def : Pat<(v8i16 (AArch64uaddv (v8i16 (zext (v8i8 V64:$op))))),
+ (v8i16 (SUBREG_TO_REG (i64 0), (UADDLVv8i8v V64:$op), hsub))>;
+def : Pat<(v4i32 (AArch64uaddv (v4i32 (sext (v4i16 V64:$op))))),
+ (v4i32 (SUBREG_TO_REG (i64 0), (SADDLVv4i16v V64:$op), ssub))>;
+def : Pat<(v4i32 (AArch64uaddv (v4i32 (zext (v4i16 V64:$op))))),
+ (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv4i16v V64:$op), ssub))>;
+
multiclass SIMDAcrossLaneLongPairIntrinsic<string Opc, SDPatternOperator addlp> {
// Patterns for addv(addlp(x)) ==> addlv
def : Pat<(i32 (vector_extract (v8i16 (insert_subvector undef,
@@ -7370,7 +7383,7 @@ multiclass SIMDAcrossLaneLongPairIntrinsic<string Opc, SDPatternOperator addlp>
def : Pat<(v4i32 (AArch64uaddv (v4i32 (addlp (v8i16 V128:$op))))),
(INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (!cast<Instruction>(Opc#"v8i16v") V128:$op), ssub)>;
- // Patterns for addp(addlp(x))) ==> addlv
+ // Patterns for addp(addlp(x)) ==> addlv
def : Pat<(v2i32 (AArch64uaddv (v2i32 (addlp (v4i16 V64:$op))))),
(INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (!cast<Instruction>(Opc#"v4i16v") V64:$op), ssub)>;
def : Pat<(v2i64 (AArch64uaddv (v2i64 (addlp (v4i32 V128:$op))))),
diff --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index cc8568709ea21..fe4657186cd2a 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -443,8 +443,8 @@ define i32 @sabd8h_rdx(<8 x i16> %a, <8 x i16> %b) {
define i32 @uabdl4s_rdx_i32(<4 x i16> %a, <4 x i16> %b) {
; CHECK-SD-LABEL: uabdl4s_rdx_i32:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: uabdl.4s v0, v0, v1
-; CHECK-SD-NEXT: addv.4s s0, v0
+; CHECK-SD-NEXT: uabd.4h v0, v0, v1
+; CHECK-SD-NEXT: uaddlv.4h s0, v0
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/neon-dotreduce.ll b/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
index 8e12446164e89..6fb4e219d39f4 100644
--- a/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+++ b/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
@@ -87,8 +87,7 @@ define i32 @test_udot_v4i8_nomla(ptr nocapture readonly %a1) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-SD-NEXT: addv s0, v0.4s
+; CHECK-SD-NEXT: uaddlv s0, v0.4h
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-add.ll b/llvm/test/CodeGen/AArch64/vecreduce-add.ll
index c72d00e65fcab..fd24282366282 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-add.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-add.ll
@@ -141,18 +141,11 @@ entry:
}
define i32 @add_v4i16_v4i32_zext(<4 x i16> %x) {
-; CHECK-SD-LABEL: add_v4i16_v4i32_zext:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-SD-NEXT: addv s0, v0.4s
-; CHECK-SD-NEXT: fmov w0, s0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: add_v4i16_v4i32_zext:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: uaddlv s0, v0.4h
-; CHECK-GI-NEXT: fmov w0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: add_v4i16_v4i32_zext:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uaddlv s0, v0.4h
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
entry:
%xx = zext <4 x i16> %x to <4 x i32>
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
@@ -160,18 +153,11 @@ entry:
}
define i32 @add_v4i16_v4i32_sext(<4 x i16> %x) {
-; CHECK-SD-LABEL: add_v4i16_v4i32_sext:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0
-; CHECK-SD-NEXT: addv s0, v0.4s
-; CHECK-SD-NEXT: fmov w0, s0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: add_v4i16_v4i32_sext:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: saddlv s0, v0.4h
-; CHECK-GI-NEXT: fmov w0, s0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: add_v4i16_v4i32_sext:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: saddlv s0, v0.4h
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
entry:
%xx = sext <4 x i16> %x to <4 x i32>
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
@@ -483,8 +469,7 @@ define i32 @add_v4i8_v4i32_zext(<4 x i8> %x) {
; CHECK-SD-LABEL: add_v4i8_v4i32_zext:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
-; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-SD-NEXT: addv s0, v0.4s
+; CHECK-SD-NEXT: uaddlv s0, v0.4h
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
@@ -589,8 +574,7 @@ entry:
define signext i16 @add_v8i8_v8i16_sext(<8 x i8> %x) {
; CHECK-SD-LABEL: add_v8i8_v8i16_sext:
; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-SD-NEXT: addv h0, v0.8h
+; CHECK-SD-NEXT: saddlv h0, v0.8b
; CHECK-SD-NEXT: smov w0, v0.h[0]
; CHECK-SD-NEXT: ret
;
@@ -939,20 +923,12 @@ entry:
}
define i32 @add_v4i16_v4i32_acc_zext(<4 x i16> %x, i32 %a) {
-; CHECK-SD-LABEL: add_v4i16_v4i32_acc_zext:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-SD-NEXT: addv s0, v0.4s
-; CHECK-SD-NEXT: fmov w8, s0
-; CHECK-SD-NEXT: add w0, w8, w0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: add_v4i16_v4i32_acc_zext:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: uaddlv s0, v0.4h
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: add w0, w8, w0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: add_v4i16_v4i32_acc_zext:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uaddlv s0, v0.4h
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: add w0, w8, w0
+; CHECK-NEXT: ret
entry:
%xx = zext <4 x i16> %x to <4 x i32>
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
@@ -961,20 +937,12 @@ entry:
}
define i32 @add_v4i16_v4i32_acc_sext(<4 x i16> %x, i32 %a) {
-; CHECK-SD-LABEL: add_v4i16_v4i32_acc_sext:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0
-; CHECK-SD-NEXT: addv s0, v0.4s
-; CHECK-SD-NEXT: fmov w8, s0
-; CHECK-SD-NEXT: add w0, w8, w0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: add_v4i16_v4i32_acc_sext:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: saddlv s0, v0.4h
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: add w0, w8, w0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: add_v4i16_v4i32_acc_sext:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: saddlv s0, v0.4h
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: add w0, w8, w0
+; CHECK-NEXT: ret
entry:
%xx = sext <4 x i16> %x to <4 x i32>
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
@@ -1324,8 +1292,7 @@ define i32 @add_v4i8_v4i32_acc_zext(<4 x i8> %x, i32 %a) {
; CHECK-SD-LABEL: add_v4i8_v4i32_acc_zext:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
-; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-SD-NEXT: addv s0, v0.4s
+; CHECK-SD-NEXT: uaddlv s0, v0.4h
; CHECK-SD-NEXT: fmov w8, s0
; CHECK-SD-NEXT: add w0, w8, w0
; CHECK-SD-NEXT: ret
@@ -1402,22 +1369,13 @@ entry:
}
define zeroext i16 @add_v8i8_v8i16_acc_zext(<8 x i8> %x, i16 %a) {
-; CHECK-SD-LABEL: add_v8i8_v8i16_acc_zext:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-SD-NEXT: addv h0, v0.8h
-; CHECK-SD-NEXT: fmov w8, s0
-; CHECK-SD-NEXT: add w8, w8, w0
-; CHECK-SD-NEXT: and w0, w8, #0xffff
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: add_v8i8_v8i16_acc_zext:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: uaddlv h0, v0.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: add w8, w8, w0
-; CHECK-GI-NEXT: and w0, w8, #0xffff
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: add_v8i8_v8i16_acc_zext:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uaddlv h0, v0.8b
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: add w8, w8, w0
+; CHECK-NEXT: and w0, w8, #0xffff
+; CHECK-NEXT: ret
entry:
%xx = zext <8 x i8> %x to <8 x i16>
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %xx)
@@ -1426,22 +1384,13 @@ entry:
}
define signext i16 @add_v8i8_v8i16_acc_sext(<8 x i8> %x, i16 %a) {
-; CHECK-SD-LABEL: add_v8i8_v8i16_acc_sext:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-SD-NEXT: addv h0, v0.8h
-; CHECK-SD-NEXT: fmov w8, s0
-; CHECK-SD-NEXT: add w8, w8, w0
-; CHECK-SD-NEXT: sxth w0, w8
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: add_v8i8_v8i16_acc_sext:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: saddlv h0, v0.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: add w8, w8, w0
-; CHECK-GI-NEXT: sxth w0, w8
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: add_v8i8_v8i16_acc_sext:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: saddlv h0, v0.8b
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: add w8, w8, w0
+; CHECK-NEXT: sxth w0, w8
+; CHECK-NEXT: ret
entry:
%xx = sext <8 x i8> %x to <8 x i16>
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %xx)
More information about the llvm-commits
mailing list