[llvm] [WebAssembly] Enable interleaved memory accesses (PR #125696)

[Petr Penzin via llvm-commits]

================
@@ -0,0 +1,361 @@
+; RUN: opt -mattr=+simd128 -passes=loop-vectorize %s | llc -mtriple=wasm32 -mattr=+simd128 -verify-machineinstrs -o - | FileCheck %s
----------------
ppenzin wrote:

Is this really the right level of test if you are just changing TTI? This would go through both cost and scheduling models, for example. Maybe analysis test would be better?

https://github.com/llvm/llvm-project/pull/125696