[llvm] [ValueTracking] ComputeNumSignBitsImpl - add basic handling of BITCAST nodes (PR #127218)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-analysis

Author: Narayan (vortex73)

<details>
<summary>Changes</summary>

When a wider scalar/vector type containing all sign bits is bitcast to a narrower vector type, we can deduce that the resulting narrow elements will also be all sign bits. This matches existing behavior in SelectionDAG and helps optimize cases involving SSE intrinsics where sign-extended values are bitcast between different vector types.

The current implementation fails to recognize that an arithmetic right shift is redundant when applied to elements that are already known to be all sign bits. This PR improves ComputeNumSignBitsImpl to track this information through bitcasts, enabling the optimization of such cases.

```
%ext = sext <1 x i1> %cmp to <1 x i8>
  %sub = bitcast <1 x i8> %ext to <4 x i2>
  %sra = ashr <4 x i2> %sub, <i2 1, i2 1, i2 1, i2 1>
  ; Can be simplified to just:
  %sub = bitcast <1 x i8> %ext to <4 x i2>
```

Closes #<!-- -->87624

---
Full diff: https://github.com/llvm/llvm-project/pull/127218.diff


2 Files Affected:

- (modified) llvm/lib/Analysis/ValueTracking.cpp (+29) 
- (added) llvm/test/Transforms/InstCombine/compute-sign-bits-bitcast.ll (+34) 


``````````diff
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index 8a9ad55366ee7..b0b963c14f8a5 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -3922,6 +3922,35 @@ static unsigned ComputeNumSignBitsImpl(const Value *V,
   if (auto *U = dyn_cast<Operator>(V)) {
     switch (Operator::getOpcode(V)) {
     default: break;
+    case Instruction::BitCast: {
+      Value *Src = U->getOperand(0);
+      Type *SrcTy = Src->getType();
+      Type *SrcScalarTy = SrcTy->getScalarType();
+
+      if (!SrcScalarTy->isIntegerTy() && !SrcScalarTy->isFloatingPointTy())
+        break;
+
+      unsigned SrcBits = SrcTy->getScalarSizeInBits();
+
+      if ((SrcBits % TyBits) != 0)
+        break;
+
+      if (auto *DstVTy = dyn_cast<FixedVectorType>(Ty)) {
+        unsigned Scale = SrcBits / TyBits;
+
+        APInt SrcDemandedElts =
+            APInt::getSplat(DstVTy->getNumElements() / Scale, APInt(1, 1));
+
+        Tmp = ComputeNumSignBits(Src, SrcDemandedElts, Depth + 1, Q);
+        if (Tmp == SrcBits)
+          return TyBits;
+      } else {
+        Tmp = ComputeNumSignBits(Src, APInt(1, 1), Depth + 1, Q);
+        if (Tmp == SrcBits)
+          return TyBits;
+      }
+      break;
+    }
     case Instruction::SExt:
       Tmp = TyBits - U->getOperand(0)->getType()->getScalarSizeInBits();
       return ComputeNumSignBits(U->getOperand(0), DemandedElts, Depth + 1, Q) +
diff --git a/llvm/test/Transforms/InstCombine/compute-sign-bits-bitcast.ll b/llvm/test/Transforms/InstCombine/compute-sign-bits-bitcast.ll
new file mode 100644
index 0000000000000..35ba53687c646
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/compute-sign-bits-bitcast.ll
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -passes=instcombine -S < %s | FileCheck %s
+
+define i32 @test_compute_sign_bits() {
+; CHECK-LABEL: define i32 @test_compute_sign_bits() {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    ret i32 -1
+;
+entry:
+  %a = add i8 -1, 0
+  %b = bitcast i8 %a to <4 x i2>
+  %c = ashr <4 x i2> %b, <i2 1, i2 1, i2 1, i2 1>
+  %d = bitcast <4 x i2> %c to i8
+  %e = sext i8 %d to i32
+  ret i32 %e
+}
+
+; Test with sign extension to ensure proper sign bit tracking
+define <4 x i2> @test_sext_bitcast(<1 x i8> %a0, <1 x i8> %a1) {
+; CHECK-LABEL: define <4 x i2> @test_sext_bitcast(
+; CHECK-SAME: <1 x i8> [[A0:%.*]], <1 x i8> [[A1:%.*]]) {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <1 x i8> [[A0]], [[A1]]
+; CHECK-NEXT:    [[EXT:%.*]] = sext <1 x i1> [[CMP]] to <1 x i8>
+; CHECK-NEXT:    [[SUB:%.*]] = bitcast <1 x i8> [[EXT]] to <4 x i2>
+; CHECK-NEXT:    ret <4 x i2> [[SUB]]
+;
+entry:
+  %cmp = icmp sgt <1 x i8> %a0, %a1
+  %ext = sext <1 x i1> %cmp to <1 x i8>
+  %sub = bitcast <1 x i8> %ext to <4 x i2>
+  %result = ashr <4 x i2> %sub, <i2 1, i2 1, i2 1, i2 1>
+  ret <4 x i2> %result
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/127218