[llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)

[Craig Topper via llvm-commits]

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@@ -310,7 +311,12 @@ RISCVTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
 ScheduleDAGInstrs *
 RISCVTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
   ScheduleDAGMI *DAG = nullptr;
-  if (EnablePostMISchedLoadStoreClustering) {
+  const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
+  bool EnableLoadStoreClusteringForLoadStoreOpt =
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topperc wrote:

Is this change tested? `EnablePostMISchedLoadStoreClustering` is true by default and I don't see any test that turns it off.

https://github.com/llvm/llvm-project/pull/124717