[llvm] [AMDGPU][True16][CodeGen] true16 codegen pattern for fma (PR #122950)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 13 07:58:14 PST 2025
github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code. :warning:
<details>
<summary>
You can test this locally with the following command:
</summary>
``````````bash
git-clang-format --diff fc952b2a6933d746e843f468052c5a62469c2658 845ff5aab553f31d0df1fa2c8cda25391d276b67 --extensions cpp -- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp llvm/lib/CodeGen/VirtRegMap.cpp llvm/lib/Target/AMDGPU/SIFoldOperands.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.cpp llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
``````````
</details>
<details>
<summary>
View the diff from clang-format here.
</summary>
``````````diff
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 9009bbe49a..1b0ed0a496 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -529,34 +529,34 @@ MachineInstr *TwoAddressInstructionImpl::findOnlyInterestingUse(
/// to.
static MCRegister getMappedReg(Register Reg,
DenseMap<Register, Register> &RegMap) {
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
while (Reg.isVirtual()) {
DenseMap<Register, Register>::iterator SI = RegMap.find(Reg);
if (SI == RegMap.end()) {
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
return 0;
- }
+ }
Reg = SI->second;
}
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
if (Reg.isPhysical()) {
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
return Reg;
}
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
return 0;
}
/// Return true if the two registers are equal or aliased.
bool TwoAddressInstructionImpl::regsAreCompatible(Register RegA,
Register RegB) const {
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
if (RegA == RegB)
return true;
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
if (!RegA || !RegB)
return false;
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
return TRI->regsOverlap(RegA, RegB);
}
@@ -784,14 +784,14 @@ bool TwoAddressInstructionImpl::isProfitableToConv3Addr(Register RegA,
// %reg1026 = ADD %reg1024, %reg1025
// r2 = MOV %reg1026
// Turn ADD into a 3-address instruction to avoid a copy.
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
MCRegister FromRegB = getMappedReg(RegB, SrcRegMap);
if (!FromRegB)
return false;
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
MCRegister ToRegA = getMappedReg(RegA, DstRegMap);
- LLVM_DEBUG(dbgs() << ToRegA << "\n");
+ LLVM_DEBUG(dbgs() << ToRegA << "\n");
return (ToRegA && !regsAreCompatible(FromRegB, ToRegA));
}
@@ -845,7 +845,7 @@ void TwoAddressInstructionImpl::scanUses(Register DstReg) {
bool IsCopy = false;
Register NewReg;
Register Reg = DstReg;
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
while (MachineInstr *UseMI =
findOnlyInterestingUse(Reg, MBB, IsCopy, NewReg, IsDstPhys)) {
if (IsCopy && !Processed.insert(UseMI).second)
@@ -857,7 +857,7 @@ void TwoAddressInstructionImpl::scanUses(Register DstReg) {
break;
if (IsDstPhys) {
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
VirtRegPairs.push_back(NewReg);
break;
}
@@ -866,12 +866,12 @@ void TwoAddressInstructionImpl::scanUses(Register DstReg) {
Reg = NewReg;
}
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
if (!VirtRegPairs.empty()) {
unsigned ToReg = VirtRegPairs.back();
VirtRegPairs.pop_back();
while (!VirtRegPairs.empty()) {
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
unsigned FromReg = VirtRegPairs.pop_back_val();
bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
if (!isNew)
@@ -882,7 +882,7 @@ void TwoAddressInstructionImpl::scanUses(Register DstReg) {
if (!isNew)
assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
}
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
}
/// If the specified instruction is not yet processed, process it if it's a
@@ -1331,11 +1331,11 @@ bool TwoAddressInstructionImpl::tryInstructionCommute(MachineInstr *MI,
bool TwoAddressInstructionImpl::tryInstructionTransform(
MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi,
unsigned SrcIdx, unsigned DstIdx, unsigned &Dist, bool shouldOnlyCommute) {
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
if (OptLevel == CodeGenOptLevel::None)
return false;
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
MachineInstr &MI = *mi;
Register regA = MI.getOperand(DstIdx).getReg();
Register regB = MI.getOperand(SrcIdx).getReg();
@@ -1346,7 +1346,7 @@ bool TwoAddressInstructionImpl::tryInstructionTransform(
if (regA.isVirtual())
scanUses(regA);
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist);
// If the instruction is convertible to 3 Addr, instead
@@ -1377,18 +1377,18 @@ bool TwoAddressInstructionImpl::tryInstructionTransform(
regBKilled = isKilled(MI, regB, true);
}
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
if (MI.isConvertibleTo3Addr()) {
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
// This instruction is potentially convertible to a true
// three-address instruction. Check if it is profitable.
- LLVM_DEBUG(dbgs() << regBKilled << "\n");
- LLVM_DEBUG(dbgs() << regA << "\n");
- LLVM_DEBUG(dbgs() << regB << "\n");
- LLVM_DEBUG(dbgs() << isProfitableToConv3Addr(regA, regB) << "\n");
+ LLVM_DEBUG(dbgs() << regBKilled << "\n");
+ LLVM_DEBUG(dbgs() << regA << "\n");
+ LLVM_DEBUG(dbgs() << regB << "\n");
+ LLVM_DEBUG(dbgs() << isProfitableToConv3Addr(regA, regB) << "\n");
if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
// Try to convert it.
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
++NumConvertedTo3Addr;
return true; // Done with this instruction.
@@ -1914,18 +1914,18 @@ bool TwoAddressInstructionImpl::run() {
LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
SmallVectorImpl<std::pair<unsigned, unsigned>> &TiedPairs
= TiedOperands.begin()->second;
- LLVM_DEBUG(dbgs() << "TiedPairs.size" << TiedPairs.size() << "\n");
+ LLVM_DEBUG(dbgs() << "TiedPairs.size" << TiedPairs.size() << "\n");
if (TiedPairs.size() == 1) {
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
unsigned SrcIdx = TiedPairs[0].first;
unsigned DstIdx = TiedPairs[0].second;
Register SrcReg = mi->getOperand(SrcIdx).getReg();
Register DstReg = mi->getOperand(DstIdx).getReg();
- LLVM_DEBUG(dbgs() << SrcReg << "\n");
- LLVM_DEBUG(dbgs() << DstReg << "\n");
+ LLVM_DEBUG(dbgs() << SrcReg << "\n");
+ LLVM_DEBUG(dbgs() << DstReg << "\n");
if (SrcReg != DstReg &&
tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) {
- LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
// The tied operands have been eliminated or shifted further down
// the block to ease elimination. Continue processing with 'nmi'.
TiedOperands.clear();
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 0fed4773b0..c52781f2d4 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3910,7 +3910,7 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
MachineBasicBlock &MBB = *MI.getParent();
unsigned Opc = MI.getOpcode();
- LLVM_DEBUG(dbgs() << __FILE__ <<__LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
// Handle MFMA.
int NewMFMAOpc = AMDGPU::getMFMAEarlyClobberOp(Opc);
@@ -3945,7 +3945,7 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
return MIB;
}
- LLVM_DEBUG(dbgs() << __FILE__ <<__LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
if (SIInstrInfo::isWMMA(MI)) {
unsigned NewOpc = AMDGPU::mapWMMA2AddrTo3AddrOpcode(MI.getOpcode());
MachineInstrBuilder MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
@@ -3960,7 +3960,7 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
return MIB;
}
- LLVM_DEBUG(dbgs() << __FILE__ <<__LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
assert(Opc != AMDGPU::V_FMAC_F16_t16_e32 &&
Opc != AMDGPU::V_FMAC_F16_fake16_e32 &&
"V_FMAC_F16_t16/fake16_e32 is not supported and not expected to be "
@@ -3986,7 +3986,7 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
Opc == AMDGPU::V_FMAC_LEGACY_F32_e64;
bool Src0Literal = false;
- LLVM_DEBUG(dbgs() << __FILE__ <<__LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
switch (Opc) {
default:
return nullptr;
@@ -4020,7 +4020,7 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
}
}
- LLVM_DEBUG(dbgs() << __FILE__ <<__LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
MachineInstrBuilder MIB;
const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst);
const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0);
@@ -4076,7 +4076,7 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
}
};
- LLVM_DEBUG(dbgs() << __FILE__ <<__LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
int64_t Imm;
if (!Src0Literal && getFoldableImm(Src2, Imm, &DefMI)) {
unsigned NewOpc =
@@ -4101,7 +4101,7 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
return MIB;
}
}
- LLVM_DEBUG(dbgs() << __FILE__ <<__LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
unsigned NewOpc = IsFMA
? (IsF16 ? (ST.hasTrue16BitInsts()
? ST.useRealTrue16Insts()
@@ -4151,7 +4151,7 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
}
}
}
- LLVM_DEBUG(dbgs() << __FILE__ <<__LINE__ << "\n");
+ LLVM_DEBUG(dbgs() << __FILE__ << __LINE__ << "\n");
// VOP2 mac/fmac with a literal operand cannot be converted to VOP3 mad/fma
// if VOP3 does not allow a literal operand.
``````````
</details>
https://github.com/llvm/llvm-project/pull/122950
More information about the llvm-commits
mailing list