[llvm] 43780f4 - RegAllocGreedy: Use Register type
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 13 05:49:43 PST 2025
Author: Matt Arsenault
Date: 2025-02-13T20:49:27+07:00
New Revision: 43780f4f9256117f73bc89cde968b9e757734ddc
URL: https://github.com/llvm/llvm-project/commit/43780f4f9256117f73bc89cde968b9e757734ddc
DIFF: https://github.com/llvm/llvm-project/commit/43780f4f9256117f73bc89cde968b9e757734ddc.diff
LOG: RegAllocGreedy: Use Register type
Added:
Modified:
llvm/lib/CodeGen/RegAllocGreedy.cpp
llvm/lib/CodeGen/RegAllocGreedy.h
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 2e43ad78e5d9b..7c7eb2ad52b41 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -431,7 +431,7 @@ MCRegister RAGreedy::tryAssign(const LiveInterval &VirtReg,
// We can also split the virtual register in cold blocks.
if (trySplitAroundHintReg(PhysHint, VirtReg, NewVRegs, Order))
- return 0;
+ return MCRegister();
// Record the missed hint, we may be able to recover
// at the end if the surrounding allocation changed.
@@ -1189,7 +1189,7 @@ unsigned RAGreedy::calculateRegionSplitCost(const LiveInterval &VirtReg,
return BestCand;
}
-unsigned RAGreedy::doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand,
+Register RAGreedy::doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand,
bool HasCompact,
SmallVectorImpl<Register> &NewVRegs) {
SmallVector<unsigned, 8> UsedCands;
@@ -1226,7 +1226,7 @@ unsigned RAGreedy::doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand,
}
splitAroundRegion(LREdit, UsedCands);
- return 0;
+ return Register();
}
// VirtReg has a physical Hint, this function tries to split VirtReg around
@@ -1293,7 +1293,7 @@ bool RAGreedy::trySplitAroundHintReg(MCPhysReg Hint,
/// tryBlockSplit - Split a global live range around every block with uses. This
/// creates a lot of local live ranges, that will be split by tryLocalSplit if
/// they don't allocate.
-unsigned RAGreedy::tryBlockSplit(const LiveInterval &VirtReg,
+Register RAGreedy::tryBlockSplit(const LiveInterval &VirtReg,
AllocationOrder &Order,
SmallVectorImpl<Register> &NewVRegs) {
assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed");
@@ -1308,7 +1308,7 @@ unsigned RAGreedy::tryBlockSplit(const LiveInterval &VirtReg,
}
// No blocks were split.
if (LREdit.empty())
- return 0;
+ return Register();
// We did split for some blocks.
SmallVector<unsigned, 8> IntvMap;
@@ -1327,7 +1327,7 @@ unsigned RAGreedy::tryBlockSplit(const LiveInterval &VirtReg,
if (VerifyEnabled)
MF->verify(this, "After splitting live range around basic blocks", &errs());
- return 0;
+ return Register();
}
//===----------------------------------------------------------------------===//
@@ -1414,7 +1414,7 @@ static bool readsLaneSubset(const MachineRegisterInfo &MRI,
/// be moved to a larger register class.
///
/// This is similar to spilling to a larger register class.
-unsigned RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
+Register RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
AllocationOrder &Order,
SmallVectorImpl<Register> &NewVRegs) {
const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg());
@@ -1469,7 +1469,7 @@ unsigned RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
if (LREdit.empty()) {
LLVM_DEBUG(dbgs() << "All uses were copies.\n");
- return 0;
+ return Register();
}
SmallVector<unsigned, 8> IntvMap;
@@ -1477,7 +1477,7 @@ unsigned RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
DebugVars->splitRegister(VirtReg.reg(), LREdit.regs(), *LIS);
// Assign all new registers to RS_Spill. This was the last chance.
ExtraInfo->setStage(LREdit.begin(), LREdit.end(), RS_Spill);
- return 0;
+ return Register();
}
//===----------------------------------------------------------------------===//
@@ -1567,13 +1567,13 @@ void RAGreedy::calcGapWeights(MCRegister PhysReg,
/// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
/// basic block.
///
-unsigned RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
+Register RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
AllocationOrder &Order,
SmallVectorImpl<Register> &NewVRegs) {
// TODO: the function currently only handles a single UseBlock; it should be
// possible to generalize.
if (SA->getUseBlocks().size() != 1)
- return 0;
+ return Register();
const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
@@ -1754,7 +1754,7 @@ unsigned RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
// Didn't find any candidates?
if (BestBefore == NumGaps)
- return 0;
+ return Register();
LLVM_DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore] << '-'
<< Uses[BestAfter] << ", " << BestDiff << ", "
@@ -1788,7 +1788,7 @@ unsigned RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
}
++NumLocalSplits;
- return 0;
+ return Register();
}
//===----------------------------------------------------------------------===//
@@ -1798,12 +1798,12 @@ unsigned RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
/// trySplit - Try to split VirtReg or one of its interferences, making it
/// assignable.
/// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
-unsigned RAGreedy::trySplit(const LiveInterval &VirtReg, AllocationOrder &Order,
+Register RAGreedy::trySplit(const LiveInterval &VirtReg, AllocationOrder &Order,
SmallVectorImpl<Register> &NewVRegs,
const SmallVirtRegSet &FixedRegisters) {
// Ranges must be Split2 or less.
if (ExtraInfo->getStage(VirtReg) >= RS_Spill)
- return 0;
+ return Register();
// Local intervals are handled separately.
if (LIS->intervalIsInOneMBB(VirtReg)) {
@@ -1839,7 +1839,7 @@ unsigned RAGreedy::trySplit(const LiveInterval &VirtReg, AllocationOrder &Order,
//===----------------------------------------------------------------------===//
/// Return true if \p reg has any tied def operand.
-static bool hasTiedDef(MachineRegisterInfo *MRI, unsigned reg) {
+static bool hasTiedDef(MachineRegisterInfo *MRI, Register reg) {
for (const MachineOperand &MO : MRI->def_operands(reg))
if (MO.isTied())
return true;
@@ -1954,7 +1954,7 @@ bool RAGreedy::mayRecolorAllInterferences(
/// \p Depth gives the current depth of the last chance recoloring.
/// \return a physical register that can be used for VirtReg or ~0u if none
/// exists.
-unsigned RAGreedy::tryLastChanceRecoloring(const LiveInterval &VirtReg,
+Register RAGreedy::tryLastChanceRecoloring(const LiveInterval &VirtReg,
AllocationOrder &Order,
SmallVectorImpl<Register> &NewVRegs,
SmallVirtRegSet &FixedRegisters,
@@ -2058,7 +2058,7 @@ unsigned RAGreedy::tryLastChanceRecoloring(const LiveInterval &VirtReg,
LLVM_DEBUG(dbgs() << "tryRecoloringCandidates deleted a fixed register "
<< printReg(ThisVirtReg) << '\n');
FixedRegisters.erase(ThisVirtReg);
- return 0;
+ return Register();
}
LLVM_DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to "
@@ -2198,7 +2198,7 @@ MCRegister RAGreedy::tryAssignCSRFirstTime(
// We are going to spill, set CostPerUseLimit to 1 to make sure that
// we will not use a callee-saved register in tryEvict.
CostPerUseLimit = 1;
- return 0;
+ return MCRegister();
}
if (ExtraInfo->getStage(VirtReg) < RS_Split) {
// We choose pre-splitting over using the CSR for the first time if
@@ -2214,7 +2214,7 @@ MCRegister RAGreedy::tryAssignCSRFirstTime(
// Perform the actual pre-splitting.
doRegionSplit(VirtReg, BestCand, false/*HasCompact*/, NewVRegs);
- return 0;
+ return MCRegister();
}
return PhysReg;
}
@@ -2299,7 +2299,7 @@ void RAGreedy::tryHintRecoloring(const LiveInterval &VirtReg) {
// reusing PhysReg for the copy-related live-ranges. Indeed, we evicted
// some register and PhysReg may be available for the other live-ranges.
SmallSet<Register, 4> Visited;
- SmallVector<unsigned, 2> RecoloringCandidates;
+ SmallVector<Register, 2> RecoloringCandidates;
HintsInfo Info;
Register Reg = VirtReg.reg();
MCRegister PhysReg = VRM->getPhys(Reg);
@@ -2446,7 +2446,7 @@ MCRegister RAGreedy::selectOrSplitImpl(const LiveInterval &VirtReg,
}
// Non empty NewVRegs means VirtReg has been split.
if (!NewVRegs.empty())
- return 0;
+ return MCRegister();
LiveRangeStage Stage = ExtraInfo->getStage(VirtReg);
LLVM_DEBUG(dbgs() << StageName[Stage] << " Cascade "
@@ -2479,7 +2479,7 @@ MCRegister RAGreedy::selectOrSplitImpl(const LiveInterval &VirtReg,
ExtraInfo->setStage(VirtReg, RS_Split);
LLVM_DEBUG(dbgs() << "wait for second round\n");
NewVRegs.push_back(VirtReg.reg());
- return 0;
+ return MCRegister();
}
if (Stage < RS_Spill && !VirtReg.empty()) {
@@ -2529,7 +2529,7 @@ MCRegister RAGreedy::selectOrSplitImpl(const LiveInterval &VirtReg,
// The live virtual register requesting allocation was spilled, so tell
// the caller not to allocate anything during this round.
- return 0;
+ return MCRegister();
}
void RAGreedy::RAGreedyStats::report(MachineOptimizationRemarkMissed &R) {
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.h b/llvm/lib/CodeGen/RegAllocGreedy.h
index 594c481826cf0..e1ec63b4a5296 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.h
+++ b/llvm/lib/CodeGen/RegAllocGreedy.h
@@ -359,7 +359,7 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public MachineFunctionPass,
BlockFrequency &BestCost,
unsigned &NumCands, bool IgnoreCSR);
/// Perform region splitting.
- unsigned doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand,
+ Register doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand,
bool HasCompact, SmallVectorImpl<Register> &NewVRegs);
/// Try to split VirtReg around physical Hint register.
bool trySplitAroundHintReg(MCPhysReg Hint, const LiveInterval &VirtReg,
@@ -372,15 +372,15 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public MachineFunctionPass,
uint8_t &CostPerUseLimit,
SmallVectorImpl<Register> &NewVRegs);
void initializeCSRCost();
- unsigned tryBlockSplit(const LiveInterval &, AllocationOrder &,
+ Register tryBlockSplit(const LiveInterval &, AllocationOrder &,
SmallVectorImpl<Register> &);
- unsigned tryInstructionSplit(const LiveInterval &, AllocationOrder &,
+ Register tryInstructionSplit(const LiveInterval &, AllocationOrder &,
SmallVectorImpl<Register> &);
- unsigned tryLocalSplit(const LiveInterval &, AllocationOrder &,
+ Register tryLocalSplit(const LiveInterval &, AllocationOrder &,
SmallVectorImpl<Register> &);
- unsigned trySplit(const LiveInterval &, AllocationOrder &,
+ Register trySplit(const LiveInterval &, AllocationOrder &,
SmallVectorImpl<Register> &, const SmallVirtRegSet &);
- unsigned tryLastChanceRecoloring(const LiveInterval &, AllocationOrder &,
+ Register tryLastChanceRecoloring(const LiveInterval &, AllocationOrder &,
SmallVectorImpl<Register> &,
SmallVirtRegSet &, RecoloringStack &,
unsigned);
More information about the llvm-commits
mailing list