[llvm] [DAG][X86]added shrd in combineor for bzhiq+shlq+or (PR #125734)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 12 23:31:33 PST 2025
https://github.com/shalini-nik updated https://github.com/llvm/llvm-project/pull/125734
>From 625e962bc4ee99755e26713c4cae84fc1263d353 Mon Sep 17 00:00:00 2001
From: shalininikhil <shalininikhil22 at gmail.com>
Date: Tue, 4 Feb 2025 17:56:47 +0000
Subject: [PATCH 1/3] [DAG][X86]added shrd in combineor for bzhiq+shlq+or
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 29 +++++++++++++++++++
.../X86/shrdq-to-insert-into-bitfield.ll | 18 ++++++++++++
2 files changed, 47 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/shrdq-to-insert-into-bitfield.ll
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a956074e50d86..395c0f5504d1b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -51887,6 +51887,35 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
}
}
+ if (N0.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SHL){
+ SDValue SHL = (N0.getOpcode() == ISD::SHL) ? N0 : N1;
+ SDValue OtherOp = (N0.getOpcode() == ISD::SHL) ? N1 : N0;
+
+ if (OtherOp.getOpcode() == ISD::AND) {
+ SDValue andop = OtherOp;
+
+ if(andop.getOperand(0).getOpcode()==ISD::Constant||andop.getOperand(1).getOpcode()==ISD::Constant){
+
+ SDValue constOp = andop.getOperand(0).getOpcode()==ISD::Constant ? andop.getOperand(0): andop.getOperand(1);
+ SDValue valueOp = andop.getOperand(0).getOpcode()==ISD::Constant ? andop.getOperand(1): andop.getOperand(0);
+ auto *ConstRHS = dyn_cast<ConstantSDNode>(constOp);
+ uint64_t maskValue = ConstRHS->getZExtValue();
+ auto *ConstSHL = dyn_cast<ConstantSDNode>(SHL.getOperand(1));
+ uint64_t shiftValue = ConstSHL->getZExtValue();
+
+ if((((uint64_t)1<<shiftValue)-1)==maskValue){
+ unsigned numbits = SHL.getScalarValueSizeInBits();
+ unsigned newshift=numbits-shiftValue;
+
+ SDValue newSHL = DAG.getNode(ISD::SHL,dl,VT,valueOp,DAG.getConstant(newshift, dl, MVT::i8));
+ SDValue R = DAG.getNode(ISD::FSHR,dl,VT,
+ SHL.getOperand(0),newSHL,DAG.getConstant(newshift, dl, MVT::i8));
+ return R;
+ }
+ }
+ }
+ }
+
if (SDValue SetCC = combineAndOrForCcmpCtest(N, DAG, DCI, Subtarget))
return SetCC;
diff --git a/llvm/test/CodeGen/X86/shrdq-to-insert-into-bitfield.ll b/llvm/test/CodeGen/X86/shrdq-to-insert-into-bitfield.ll
new file mode 100644
index 0000000000000..cc205ee145d88
--- /dev/null
+++ b/llvm/test/CodeGen/X86/shrdq-to-insert-into-bitfield.ll
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O3 < %s | FileCheck %s
+
+define dso_local i64 @updateTop10Bits(i64 noundef %A, i64 noundef %B) local_unnamed_addr #0 {
+; CHECK-LABEL: updateTop10Bits:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: shlq $10, %rax
+; CHECK-NEXT: shrdq $10, %rsi, %rax
+; CHECK-NEXT: retq
+entry:
+ %and = and i64 %A, 18014398509481983
+ %shl = shl i64 %B, 54
+ %or = or disjoint i64 %shl, %and
+ ret i64 %or
+}
+
+attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="skylake" "target-features"="+adx,+aes,+avx,+avx2,+bmi,+bmi2,+clflushopt,+cmov,+crc32,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sgx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" }
\ No newline at end of file
>From c4b87398da054139412e2e69037e8a5b5d7df39f Mon Sep 17 00:00:00 2001
From: shalininikhil <shalininikhil22 at gmail.com>
Date: Wed, 5 Feb 2025 12:16:54 +0000
Subject: [PATCH 2/3] using sd_match to match this pattern
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 39 ++++++++-----------------
1 file changed, 12 insertions(+), 27 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 395c0f5504d1b..c4624f9e1a5d5 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -51887,33 +51887,18 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
}
}
- if (N0.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SHL){
- SDValue SHL = (N0.getOpcode() == ISD::SHL) ? N0 : N1;
- SDValue OtherOp = (N0.getOpcode() == ISD::SHL) ? N1 : N0;
-
- if (OtherOp.getOpcode() == ISD::AND) {
- SDValue andop = OtherOp;
-
- if(andop.getOperand(0).getOpcode()==ISD::Constant||andop.getOperand(1).getOpcode()==ISD::Constant){
-
- SDValue constOp = andop.getOperand(0).getOpcode()==ISD::Constant ? andop.getOperand(0): andop.getOperand(1);
- SDValue valueOp = andop.getOperand(0).getOpcode()==ISD::Constant ? andop.getOperand(1): andop.getOperand(0);
- auto *ConstRHS = dyn_cast<ConstantSDNode>(constOp);
- uint64_t maskValue = ConstRHS->getZExtValue();
- auto *ConstSHL = dyn_cast<ConstantSDNode>(SHL.getOperand(1));
- uint64_t shiftValue = ConstSHL->getZExtValue();
-
- if((((uint64_t)1<<shiftValue)-1)==maskValue){
- unsigned numbits = SHL.getScalarValueSizeInBits();
- unsigned newshift=numbits-shiftValue;
-
- SDValue newSHL = DAG.getNode(ISD::SHL,dl,VT,valueOp,DAG.getConstant(newshift, dl, MVT::i8));
- SDValue R = DAG.getNode(ISD::FSHR,dl,VT,
- SHL.getOperand(0),newSHL,DAG.getConstant(newshift, dl, MVT::i8));
- return R;
- }
- }
- }
+ using namespace llvm::SDPatternMatch;
+ APInt MaskConst,ShlConst;
+ SDValue A, B;
+ if(sd_match(N,m_Or(m_Shl(m_Value(B),m_ConstInt(ShlConst)),m_And(m_Value(A),m_ConstInt(MaskConst))))){
+ uint64_t shiftValue = ShlConst.getZExtValue();
+ if(MaskConst.isMask(shiftValue)){
+ unsigned numbits = B.getScalarValueSizeInBits();
+ unsigned newshift=numbits-shiftValue;
+ SDValue newSHL = DAG.getNode(ISD::SHL,dl,VT,A,DAG.getConstant(newshift, dl, MVT::i8));
+ SDValue R = DAG.getNode(ISD::FSHR,dl,VT,B,newSHL,DAG.getConstant(newshift, dl, MVT::i8));
+ return R;
+ }
}
if (SDValue SetCC = combineAndOrForCcmpCtest(N, DAG, DCI, Subtarget))
>From 6d3f1145c1c1b9c05feb9e94d03f85b6b96242e0 Mon Sep 17 00:00:00 2001
From: shalini-nik <shalininikhil22 at gmail.com>
Date: Thu, 13 Feb 2025 13:00:37 +0530
Subject: [PATCH 3/3] formated the code with clang-format and Replaced both
getConstant with getShiftAmountConstant
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c4624f9e1a5d5..c283974dd91de 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -51891,12 +51891,14 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
APInt MaskConst,ShlConst;
SDValue A, B;
if(sd_match(N,m_Or(m_Shl(m_Value(B),m_ConstInt(ShlConst)),m_And(m_Value(A),m_ConstInt(MaskConst))))){
- uint64_t shiftValue = ShlConst.getZExtValue();
- if(MaskConst.isMask(shiftValue)){
- unsigned numbits = B.getScalarValueSizeInBits();
- unsigned newshift=numbits-shiftValue;
- SDValue newSHL = DAG.getNode(ISD::SHL,dl,VT,A,DAG.getConstant(newshift, dl, MVT::i8));
- SDValue R = DAG.getNode(ISD::FSHR,dl,VT,B,newSHL,DAG.getConstant(newshift, dl, MVT::i8));
+ uint64_t ShiftValue = ShlConst.getZExtValue();
+ if (MaskConst.isMask(ShiftValue)) {
+ unsigned NumBits = B.getScalarValueSizeInBits();
+ unsigned NewShift = NumBits - ShiftValue;
+ SDValue NewSHL = DAG.getNode(
+ ISD::SHL, dl, VT, A, DAG.getShiftAmountConstant(NewShift, VT, dl));
+ SDValue R = DAG.getNode(ISD::FSHR, dl, VT, B, NewSHL,
+ DAG.getShiftAmountConstant(NewShift, VT, dl));
return R;
}
}
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