[llvm] [PowerPC] Optimize BUILD_VECTOR from load and zeros (PR #126599)

[Nemanja Ivanovic via llvm-commits]

https://github.com/nemanjai commented:

The pattern seems somewhat obscure, but it clearly appears in some important code if it warrants a patch like this.
Overall, I think this is a nice patch, but I wonder if it could be much simpler if we address this in a DAG combine and add a custom PPCISD node.
What I mean is that we add a node for example `PPCISD::VEC_INS_VAL_IN_ZEROS val, idx` where we would detect that this pattern inserts a single value into a vector while zeroing out the remaining values. This would simplify the matching code in the td file and make it more obvious if there are any holes. For example, this can probably improve even for situations where the `val` is already in a register - see https://godbolt.org/z/PP4WY6996

My code generation suggestions there certainly seem simpler, but TBH, I haven't looked at the UM to see if they improve latency.

P.S. The definition and uses of `SplatAndAssignIndexed` are nice demonstrations of your tblgen-fu! :)

https://github.com/llvm/llvm-project/pull/126599