[llvm] [AMDGPU] Set inst_pref_size to maximum (PR #126981)
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Wed Feb 12 14:17:17 PST 2025
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git-clang-format --diff 76392421553f3b25552970812868f70721971451 ddd77604df9e273fc963d7defad012f1fafca2e1 --extensions cpp,h -- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h llvm/lib/Target/AMDGPU/SIProgramInfo.cpp llvm/lib/Target/AMDGPU/SIProgramInfo.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AMDGPU/SIProgramInfo.h b/llvm/lib/Target/AMDGPU/SIProgramInfo.h
index 2836af033d..3f68b0255a 100644
--- a/llvm/lib/Target/AMDGPU/SIProgramInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIProgramInfo.h
@@ -30,88 +30,88 @@ class MachineFunction;
/// Track resource usage for kernels / entry functions.
struct LLVM_EXTERNAL_VISIBILITY SIProgramInfo {
- std::optional<uint64_t> CodeSizeInBytes;
-
- // Fields set in PGM_RSRC1 pm4 packet.
- const MCExpr *VGPRBlocks = nullptr;
- const MCExpr *SGPRBlocks = nullptr;
- uint32_t Priority = 0;
- uint32_t FloatMode = 0;
- uint32_t Priv = 0;
- uint32_t DX10Clamp = 0;
- uint32_t DebugMode = 0;
- uint32_t IEEEMode = 0;
- uint32_t WgpMode = 0; // GFX10+
- uint32_t MemOrdered = 0; // GFX10+
- uint32_t RrWgMode = 0; // GFX12+
- const MCExpr *ScratchSize = nullptr;
-
- // State used to calculate fields set in PGM_RSRC2 pm4 packet.
- uint32_t LDSBlocks = 0;
- const MCExpr *ScratchBlocks = nullptr;
-
- // Fields set in PGM_RSRC2 pm4 packet
- const MCExpr *ScratchEnable = nullptr;
- uint32_t UserSGPR = 0;
- uint32_t TrapHandlerEnable = 0;
- uint32_t TGIdXEnable = 0;
- uint32_t TGIdYEnable = 0;
- uint32_t TGIdZEnable = 0;
- uint32_t TGSizeEnable = 0;
- uint32_t TIdIGCompCount = 0;
- uint32_t EXCPEnMSB = 0;
- uint32_t LdsSize = 0;
- uint32_t EXCPEnable = 0;
-
- const MCExpr *ComputePGMRSrc3 = nullptr;
-
- const MCExpr *NumVGPR = nullptr;
- const MCExpr *NumArchVGPR = nullptr;
- const MCExpr *NumAccVGPR = nullptr;
- const MCExpr *AccumOffset = nullptr;
- uint32_t TgSplit = 0;
- const MCExpr *NumSGPR = nullptr;
- unsigned SGPRSpill = 0;
- unsigned VGPRSpill = 0;
- uint32_t LDSSize = 0;
- const MCExpr *FlatUsed = nullptr;
-
- // Number of SGPRs that meets number of waves per execution unit request.
- const MCExpr *NumSGPRsForWavesPerEU = nullptr;
-
- // Number of VGPRs that meets number of waves per execution unit request.
- const MCExpr *NumVGPRsForWavesPerEU = nullptr;
-
- // Final occupancy.
- const MCExpr *Occupancy = nullptr;
-
- // Whether there is recursion, dynamic allocas, indirect calls or some other
- // reason there may be statically unknown stack usage.
- const MCExpr *DynamicCallStack = nullptr;
-
- // Bonus information for debugging.
- const MCExpr *VCCUsed = nullptr;
-
- SIProgramInfo() = default;
-
- // The constructor sets the values for each member as shown in the struct.
- // However, setting the MCExpr members to their zero value equivalent
- // happens in reset together with (duplicated) value re-set for the
- // non-MCExpr members.
- void reset(const MachineFunction &MF);
-
- // Get function code size and cache the value.
- uint64_t getFunctionCodeSize(const MachineFunction &MF);
-
- /// Compute the value of the ComputePGMRsrc1 register.
- const MCExpr *getComputePGMRSrc1(const GCNSubtarget &ST,
- MCContext &Ctx) const;
- const MCExpr *getPGMRSrc1(CallingConv::ID CC, const GCNSubtarget &ST,
- MCContext &Ctx) const;
-
- /// Compute the value of the ComputePGMRsrc2 register.
- const MCExpr *getComputePGMRSrc2(MCContext &Ctx) const;
- const MCExpr *getPGMRSrc2(CallingConv::ID CC, MCContext &Ctx) const;
+ std::optional<uint64_t> CodeSizeInBytes;
+
+ // Fields set in PGM_RSRC1 pm4 packet.
+ const MCExpr *VGPRBlocks = nullptr;
+ const MCExpr *SGPRBlocks = nullptr;
+ uint32_t Priority = 0;
+ uint32_t FloatMode = 0;
+ uint32_t Priv = 0;
+ uint32_t DX10Clamp = 0;
+ uint32_t DebugMode = 0;
+ uint32_t IEEEMode = 0;
+ uint32_t WgpMode = 0; // GFX10+
+ uint32_t MemOrdered = 0; // GFX10+
+ uint32_t RrWgMode = 0; // GFX12+
+ const MCExpr *ScratchSize = nullptr;
+
+ // State used to calculate fields set in PGM_RSRC2 pm4 packet.
+ uint32_t LDSBlocks = 0;
+ const MCExpr *ScratchBlocks = nullptr;
+
+ // Fields set in PGM_RSRC2 pm4 packet
+ const MCExpr *ScratchEnable = nullptr;
+ uint32_t UserSGPR = 0;
+ uint32_t TrapHandlerEnable = 0;
+ uint32_t TGIdXEnable = 0;
+ uint32_t TGIdYEnable = 0;
+ uint32_t TGIdZEnable = 0;
+ uint32_t TGSizeEnable = 0;
+ uint32_t TIdIGCompCount = 0;
+ uint32_t EXCPEnMSB = 0;
+ uint32_t LdsSize = 0;
+ uint32_t EXCPEnable = 0;
+
+ const MCExpr *ComputePGMRSrc3 = nullptr;
+
+ const MCExpr *NumVGPR = nullptr;
+ const MCExpr *NumArchVGPR = nullptr;
+ const MCExpr *NumAccVGPR = nullptr;
+ const MCExpr *AccumOffset = nullptr;
+ uint32_t TgSplit = 0;
+ const MCExpr *NumSGPR = nullptr;
+ unsigned SGPRSpill = 0;
+ unsigned VGPRSpill = 0;
+ uint32_t LDSSize = 0;
+ const MCExpr *FlatUsed = nullptr;
+
+ // Number of SGPRs that meets number of waves per execution unit request.
+ const MCExpr *NumSGPRsForWavesPerEU = nullptr;
+
+ // Number of VGPRs that meets number of waves per execution unit request.
+ const MCExpr *NumVGPRsForWavesPerEU = nullptr;
+
+ // Final occupancy.
+ const MCExpr *Occupancy = nullptr;
+
+ // Whether there is recursion, dynamic allocas, indirect calls or some other
+ // reason there may be statically unknown stack usage.
+ const MCExpr *DynamicCallStack = nullptr;
+
+ // Bonus information for debugging.
+ const MCExpr *VCCUsed = nullptr;
+
+ SIProgramInfo() = default;
+
+ // The constructor sets the values for each member as shown in the struct.
+ // However, setting the MCExpr members to their zero value equivalent
+ // happens in reset together with (duplicated) value re-set for the
+ // non-MCExpr members.
+ void reset(const MachineFunction &MF);
+
+ // Get function code size and cache the value.
+ uint64_t getFunctionCodeSize(const MachineFunction &MF);
+
+ /// Compute the value of the ComputePGMRsrc1 register.
+ const MCExpr *getComputePGMRSrc1(const GCNSubtarget &ST,
+ MCContext &Ctx) const;
+ const MCExpr *getPGMRSrc1(CallingConv::ID CC, const GCNSubtarget &ST,
+ MCContext &Ctx) const;
+
+ /// Compute the value of the ComputePGMRsrc2 register.
+ const MCExpr *getComputePGMRSrc2(MCContext &Ctx) const;
+ const MCExpr *getPGMRSrc2(CallingConv::ID CC, MCContext &Ctx) const;
};
} // namespace llvm
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https://github.com/llvm/llvm-project/pull/126981
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