[llvm] [TableGen] Add support for per-write cycle tunables (PR #125870)

[Rahul Joshi via llvm-commits]

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@@ -1308,23 +1308,30 @@ void SubtargetEmitter::genSchedClassTables(const CodeGenProcModel &ProcModel,
       }
       ConstRecVec ValidWrites =
           ReadAdvance->getValueAsListOfDefs("ValidWrites");
-      IdxVec WriteIDs;
+      std::vector<int64_t> CycleTunables =
+          ReadAdvance->getValueAsListOfInts("CycleTunables");
+      std::vector<std::pair<unsigned, int>> WriteIDs;
+      if (CycleTunables.size() > ValidWrites.size())
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jurahul wrote:

Can this instead be made an assert `ProcReadAdvance` class. Then we don't need special logic in the Subtarget emitter

https://github.com/llvm/llvm-project/pull/125870