[llvm] [AMDGPU][LIT][NFC] Added test for live-in CSR SGPR used partially giving MachineVerifier error (PR #126696)
Vikash Gupta via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 12 07:19:30 PST 2025
https://github.com/vg0204 updated https://github.com/llvm/llvm-project/pull/126696
>From 12c07f5a5ddec92aeb0da27f6cf7ef191e349360 Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Tue, 11 Feb 2025 08:13:39 +0000
Subject: [PATCH 1/3] [AMDGPU][LIT][NFC] Added xfail test for live-in CSR SGPR
used partially
---
.../spill-partial-csr-sgpr-live-ins.mir | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
diff --git a/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir b/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
new file mode 100644
index 0000000000000..8ed88339d5918
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
@@ -0,0 +1,52 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s
+# XFAIL: *
+
+# FIXME : Currently, MRI's liveIn check for regiters does not take corresponding live-in's sub-registers in account. As a result
+# in SILowerSGPRSpills, the SubReg spill gets marked KILLED eventhough its SuperReg is in function Live-ins. This causes machine
+# verifier to now fail at direct usage of that SubReg, which intially should not be any problem before adding spill.
+
+# CHECK: *** Bad machine code: Using an undefined physical register ***
+
+---
+name: spill_partial_live_csr_sgpr_argument_test_1
+tracksRegLiveness: true
+liveins:
+ - { reg: '$sgpr50_sgpr51' }
+body: |
+ bb.0:
+ liveins: $sgpr50_sgpr51
+
+ S_NOP 0, implicit $sgpr50
+ $sgpr50 = S_MOV_B32 0
+
+...
+
+---
+name: spill_partial_live_csr_sgpr_argument_test_2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$sgpr50_sgpr51' }
+body: |
+ bb.0:
+ liveins: $sgpr50_sgpr51
+
+ S_NOP 0, implicit $sgpr50
+ $sgpr50_sgpr51 = S_MOV_B64 0
+
+...
+
+---
+name: spill_partial_live_csr_sgpr_argument_test_3
+tracksRegLiveness: true
+liveins:
+ - { reg: '$sgpr52_sgpr53' }
+body: |
+ bb.0:
+ liveins: $sgpr52_sgpr53
+
+ S_NOP 0, implicit $sgpr53
+ $sgpr52_sgpr53 = S_MOV_B64 0
+ $sgpr54 = S_MOV_B32 0
+
+...
>From c9943c00f96f742ea3186c69a0ac8069389e33a6 Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Tue, 11 Feb 2025 09:19:21 +0000
Subject: [PATCH 2/3] Modefied xfail test into normal test with verifier check
line.
---
.../CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir b/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
index 8ed88339d5918..a521ba8ec0be5 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
@@ -1,12 +1,11 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s
-# XFAIL: *
+# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills %s -o /dev/null 2>&1 | FileCheck -check-prefix=VERIFIER %s
-# FIXME : Currently, MRI's liveIn check for regiters does not take corresponding live-in's sub-registers in account. As a result
-# in SILowerSGPRSpills, the SubReg spill gets marked KILLED eventhough its SuperReg is in function Live-ins. This causes machine
+# FIXME : Currently, MRI's liveIn check for registers does not take the corresponding live-in's sub-registers into account. As a result
+# in SILowerSGPRSpills, the SubReg spill gets marked KILLED even though its SuperReg is in the function Live-ins. This causes machine
# verifier to now fail at direct usage of that SubReg, which intially should not be any problem before adding spill.
-# CHECK: *** Bad machine code: Using an undefined physical register ***
+# VERIFIER: *** Bad machine code: Using an undefined physical register ***
---
name: spill_partial_live_csr_sgpr_argument_test_1
>From e7aaf4a8e9b13376f9ceb6a41b3c53d5ca612884 Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Wed, 12 Feb 2025 15:18:56 +0000
Subject: [PATCH 3/3] Merged all functions into one to facilitate each tests.
---
.../spill-partial-csr-sgpr-live-ins.mir | 49 +++++++------------
1 file changed, 19 insertions(+), 30 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir b/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
index a521ba8ec0be5..47d0f3c0aacf5 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
@@ -6,46 +6,35 @@
# verifier to now fail at direct usage of that SubReg, which intially should not be any problem before adding spill.
# VERIFIER: *** Bad machine code: Using an undefined physical register ***
+# VERIFIER: - instruction: S_NOP 0, implicit $sgpr50
+# VERIFIER-NEXT: - operand 1: implicit $sgpr50
----
-name: spill_partial_live_csr_sgpr_argument_test_1
-tracksRegLiveness: true
-liveins:
- - { reg: '$sgpr50_sgpr51' }
-body: |
- bb.0:
- liveins: $sgpr50_sgpr51
-
- S_NOP 0, implicit $sgpr50
- $sgpr50 = S_MOV_B32 0
+# VERIFIER: *** Bad machine code: Using an undefined physical register ***
+# VERIFIER: - instruction: S_NOP 0, implicit $sgpr52
+# VERIFIER-NEXT: - operand 1: implicit $sgpr52
-...
+# VERIFIER: *** Bad machine code: Using an undefined physical register ***
+# VERIFIER: - instruction: S_NOP 0, implicit $sgpr55
+# VERIFIER-NEXT: - operand 1: implicit $sgpr55
+# VERIFIER: LLVM ERROR: Found 3 machine code errors.
---
-name: spill_partial_live_csr_sgpr_argument_test_2
+name: spill_partial_live_csr_sgpr_test
tracksRegLiveness: true
liveins:
- { reg: '$sgpr50_sgpr51' }
-body: |
- bb.0:
- liveins: $sgpr50_sgpr51
-
- S_NOP 0, implicit $sgpr50
- $sgpr50_sgpr51 = S_MOV_B64 0
-
-...
-
----
-name: spill_partial_live_csr_sgpr_argument_test_3
-tracksRegLiveness: true
-liveins:
- { reg: '$sgpr52_sgpr53' }
+ - { reg: '$sgpr54_sgpr55' }
body: |
bb.0:
- liveins: $sgpr52_sgpr53
+ liveins: $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55
- S_NOP 0, implicit $sgpr53
+ S_NOP 0, implicit $sgpr50
+ $sgpr50 = S_MOV_B32 0
+ S_NOP 0, implicit $sgpr52
$sgpr52_sgpr53 = S_MOV_B64 0
- $sgpr54 = S_MOV_B32 0
-
+ S_NOP 0, implicit $sgpr55
+ $sgpr54_sgpr55 = S_MOV_B64 0
+ $sgpr56 = S_MOV_B32 0
...
+
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