[llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)

[Djordje Todorovic via llvm-commits]

djtodoro wrote:

One part of the 32-bit extension that NXP will upstream soon can easily be extended on top of this optimization, and I do not see any conflict with this. cc @lenary @anmolparalkar-nxp

https://github.com/llvm/llvm-project/pull/124717