[llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)

[Djordje Todorovic via llvm-commits]

djtodoro wrote:

> I'm pretty sure some of this is copied from AArch64. That's a helpful thing to mention in the description as it makes it easier to review if we can cross reference the prior art. Can you mention any notable differences?

I have added a top-level comment that explains this. Basically, we use `tryToPairLdStInst` from it only. AArch64 performs away more things, and it can be future work for RISC-V as well. 

https://github.com/llvm/llvm-project/pull/124717