[llvm] [MachineScheduler][RISCV] Release the pending queue base on condition (PR #125468)

[Piyou Chen via llvm-commits]

BeMg wrote:

I think we can close this pull request now and wait the example that make real cpu exist spill issue (between hazard and register pressure).

Thank you all for your review comments. :)

https://github.com/llvm/llvm-project/pull/125468