[llvm] [ARM] Fix calling convention for __fp16 with big-endian (PR #126741)

[Eli Friedman via llvm-commits]

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@@ -15257,10 +15275,19 @@ static SDValue PerformVMOVhrCombine(SDNode *N,
   // fold (VMOVhr (load x)) -> (load (f16*)x)
   if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(Op0)) {
     if (LN0->hasOneUse() && LN0->isUnindexed() &&
-        LN0->getMemoryVT() == MVT::i16) {
-      SDValue Load =
-          DCI.DAG.getLoad(N->getValueType(0), SDLoc(N), LN0->getChain(),
-                          LN0->getBasePtr(), LN0->getMemOperand());
+        (LN0->getMemoryVT() == MVT::i16 || LN0->getMemoryVT() == MVT::i32)) {
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efriedma-quic wrote:

Maybe instead of hacking this, make the call lowering code generate a 16-bit load?

If you are going to mess with the width of the load, you need an `LN0->isSimple()` check.

https://github.com/llvm/llvm-project/pull/126741