[llvm] [Aarch64] [ISel] Don't save vaargs registers if vaargs are unused (PR #126780)
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Tue Feb 11 10:58:20 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Pavel Skripkin (pskrgag)
<details>
<summary>Changes</summary>
If vaargs are not used there is no need to save them. LLVM already implements such optimization for x86, as well as gcc [1].
Some ABI tests are kept almost as-is, except for stack offsets, by just adding llvm.va_start. Only laapcs_vararg_frame.ll test was rewritten to match new behavior.
[1] https://godbolt.org/z/GWWKr8xMd
---
Full diff: https://github.com/llvm/llvm-project/pull/126780.diff
7 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/aapcs_vararg_frame.ll (+4-14)
- (modified) llvm/test/CodeGen/AArch64/alloca.ll (+7-6)
- (modified) llvm/test/CodeGen/AArch64/arm64ec-hybrid-patchable.ll (-4)
- (modified) llvm/test/CodeGen/AArch64/darwinpcs-tail.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/vararg-tallcall.ll (+4-2)
- (modified) llvm/test/CodeGen/AArch64/win64_vararg2.ll (+4-7)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 34464d317beaf..5103374e14d80 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -8189,7 +8189,7 @@ SDValue AArch64TargetLowering::LowerFormalArguments(
}
// varargs
- if (isVarArg) {
+ if (isVarArg && DAG.getMachineFunction().getFrameInfo().hasVAStart()) {
if (!Subtarget->isTargetDarwin() || IsWin64) {
// The AAPCS variadic function ABI is identical to the non-variadic
// one. As a result there may be more arguments in registers and we should
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/aapcs_vararg_frame.ll b/llvm/test/CodeGen/AArch64/GlobalISel/aapcs_vararg_frame.ll
index 7892e892a2412..ddc4347950b27 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/aapcs_vararg_frame.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/aapcs_vararg_frame.ll
@@ -3,22 +3,12 @@
; RUN: llc < %s --global-isel=1 -mtriple=aarch64-linux-gnu -mattr=+fp-armv8 | FileCheck %s --check-prefix=GISEL
define void @va(i32 %count, half %f, ...) nounwind {
-; CHECK-LABEL: va:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #176
-; CHECK-NEXT: stp x2, x3, [sp, #128]
-; CHECK-NEXT: str x1, [sp, #120]
-; CHECK-NEXT: stp x4, x5, [sp, #144]
-; CHECK-NEXT: stp x6, x7, [sp, #160]
-; CHECK-NEXT: stp q1, q2, [sp]
-; CHECK-NEXT: stp q3, q4, [sp, #32]
-; CHECK-NEXT: stp q5, q6, [sp, #64]
-; CHECK-NEXT: str q7, [sp, #96]
-; CHECK-NEXT: add sp, sp, #176
+; CHECK-LABEL: va: // @va
+; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ret
;
-; GISEL-LABEL: va:
-; GISEL: // %bb.0: // %entry
+; GISEL-LABEL: va: // @va
+; GISEL: // %bb.0: // %entry
; GISEL-NEXT: sub sp, sp, #176
; GISEL-NEXT: stp x1, x2, [sp, #120]
; GISEL-NEXT: stp x3, x4, [sp, #136]
diff --git a/llvm/test/CodeGen/AArch64/alloca.ll b/llvm/test/CodeGen/AArch64/alloca.ll
index ca3a500d79f32..76b50d62ab600 100644
--- a/llvm/test/CodeGen/AArch64/alloca.ll
+++ b/llvm/test/CodeGen/AArch64/alloca.ll
@@ -82,21 +82,22 @@ define void @test_variadic_alloca(i64 %n, ...) {
; [...]
; CHECK-DAG: stp q0, q1, [x29, #-192]
-; CHECK-DAG: stp x5, x6, [x29, #-24]
+; CHECK-DAG: stp x5, x6, [x29, #-32]
; [...]
-; CHECK-DAG: stp x1, x2, [x29, #-56]
+; CHECK-DAG: stp x1, x2, [x29, #-64]
; CHECK-NOFP-ARM64: stp x29, x30, [sp, #-16]!
; CHECK-NOFP-ARM64: mov x29, sp
; CHECK-NOFP-ARM64: sub sp, sp, #64
-; CHECK-NOFP-ARM64-DAG: stp x5, x6, [x29, #-24]
+; CHECK-NOFP-ARM64-DAG: stp x5, x6, [x29, #-32]
; [...]
-; CHECK-NOFP-ARM64-DAG: stp x3, x4, [x29, #-40]
+; CHECK-NOFP-ARM64-DAG: stp x3, x4, [x29, #-48]
; [...]
-; CHECK-NOFP-ARM64-DAG: stp x1, x2, [x29, #-56]
+; CHECK-NOFP-ARM64-DAG: stp x1, x2, [x29, #-64]
; [...]
; CHECK-NOFP-ARM64: mov x8, sp
-
+ %valist = alloca i8
+ call void @llvm.va_start(ptr %valist)
%addr = alloca i8, i64 %n
call void @use_addr(ptr %addr)
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-hybrid-patchable.ll b/llvm/test/CodeGen/AArch64/arm64ec-hybrid-patchable.ll
index 1ed6a273338ab..9e2633f3f63ea 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-hybrid-patchable.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-hybrid-patchable.ll
@@ -24,10 +24,6 @@ define void @has_varargs(...) hybrid_patchable nounwind {
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: "#has_varargs$hp_target": // @"#has_varargs$hp_target"
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #32
-; CHECK-NEXT: stp x0, x1, [x4, #-32]
-; CHECK-NEXT: stp x2, x3, [x4, #-16]
-; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret
ret void
}
diff --git a/llvm/test/CodeGen/AArch64/darwinpcs-tail.ll b/llvm/test/CodeGen/AArch64/darwinpcs-tail.ll
index 5d3c755d0d73d..da176894c48a9 100644
--- a/llvm/test/CodeGen/AArch64/darwinpcs-tail.ll
+++ b/llvm/test/CodeGen/AArch64/darwinpcs-tail.ll
@@ -8,8 +8,8 @@
; CHECK-LABEL: _tailTest:
; CHECK: b __ZN1C3addEPKcz
; CHECK-LABEL: __ZThn8_N1C1fEiiiiiiiiiz:
-; CHECK: ldr w9, [sp, #4]
-; CHECK: str w9, [sp, #4]
+; CHECK: ldr w8, [sp, #4]
+; CHECK: str w8, [sp, #4]
; CHECK: b __ZN1C1fEiiiiiiiiiz
%class.C = type { %class.A.base, [4 x i8], %class.B.base, [4 x i8] }
diff --git a/llvm/test/CodeGen/AArch64/vararg-tallcall.ll b/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
index 812837639196e..6abe33ac6816e 100644
--- a/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
+++ b/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
@@ -14,6 +14,8 @@ $"??_9B@@$BA at AA" = comdat any
; Function Attrs: noinline optnone
define linkonce_odr void @"??_9B@@$BA at AA"(ptr %this, ...) #1 comdat align 2 {
entry:
+ %valist = alloca i8
+ call void @llvm.va_start.p0(ptr %valist)
%this.addr = alloca ptr, align 8
store ptr %this, ptr %this.addr, align 8
%this1 = load ptr, ptr %this.addr, align 8
@@ -37,6 +39,6 @@ attributes #1 = { noinline optnone "thunk" }
; CHECK-EC: ldr x9, [x0]
; CHECK-EC: ldr x11, [x9]
; CHECK-EC: mov v0.16b, v7.16b
-; CHECK-EC: add x4, sp, #64
-; CHECK-EC: add sp, sp, #64
+; CHECK-EC: add x4, sp, #80
+; CHECK-EC: add sp, sp, #80
; CHECK-EC: br x11
diff --git a/llvm/test/CodeGen/AArch64/win64_vararg2.ll b/llvm/test/CodeGen/AArch64/win64_vararg2.ll
index dff49148fb772..27d7d4786e4df 100644
--- a/llvm/test/CodeGen/AArch64/win64_vararg2.ll
+++ b/llvm/test/CodeGen/AArch64/win64_vararg2.ll
@@ -7,17 +7,14 @@ define i1 @va_func(i32 %a, i8 %b, i8 %c, ...) {
; CHECK-LABEL: va_func:
; CHECK: .seh_proc va_func
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #80
-; CHECK-NEXT: .seh_stackalloc 80
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: .seh_stackalloc 32
; CHECK-NEXT: str x19, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .seh_save_reg x19, 16
; CHECK-NEXT: str x30, [sp, #24] // 8-byte Folded Spill
; CHECK-NEXT: .seh_save_reg x30, 24
; CHECK-NEXT: .seh_endprologue
; CHECK-NEXT: mov w19, w0
-; CHECK-NEXT: stp x3, x4, [sp, #40]
-; CHECK-NEXT: stp x5, x6, [sp, #56]
-; CHECK-NEXT: str x7, [sp, #72]
; CHECK-NEXT: str w0, [sp, #12]
; CHECK-NEXT: strb w1, [sp, #11]
; CHECK-NEXT: strb w2, [sp, #10]
@@ -29,8 +26,8 @@ define i1 @va_func(i32 %a, i8 %b, i8 %c, ...) {
; CHECK-NEXT: .seh_save_reg x30, 24
; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: .seh_save_reg x19, 16
-; CHECK-NEXT: add sp, sp, #80
-; CHECK-NEXT: .seh_stackalloc 80
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: .seh_stackalloc 32
; CHECK-NEXT: .seh_endepilogue
; CHECK-NEXT: ret
; CHECK-NEXT: .seh_endfunclet
``````````
</details>
https://github.com/llvm/llvm-project/pull/126780
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