[llvm] [RISCV] Avoid VMNOT by swapping VMERGE operands (PR #126751)

[Piotr Fusik via llvm-commits]

https://github.com/pfusik created https://github.com/llvm/llvm-project/pull/126751

None

>From bee9440d02010bad373a1c75793618a2d1930c3d Mon Sep 17 00:00:00 2001
From: Piotr Fusik <p.fusik at samsung.com>
Date: Tue, 11 Feb 2025 16:51:05 +0100
Subject: [PATCH] [RISCV] Avoid VMNOT by swapping VMERGE operands

---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 13ce566f8def6c..c04d5f0a3ebf68 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8875,6 +8875,16 @@ SDValue RISCVTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
   MVT I1ContainerVT =
       MVT::getVectorVT(MVT::i1, ContainerVT.getVectorElementCount());
 
+  bool negated = false;
+  if (Src.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
+      Src.getOperand(0).getOpcode() ==
+          RISCVISD::VMXOR_VL) { // TODO: check xor 1
+    negated = true;
+    Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, Src.getValueType(),
+                      Src.getOperand(0).getOperand(0),
+                      DAG.getVectorIdxConstant(0, DL));
+  }
+
   SDValue CC = convertToScalableVector(I1ContainerVT, Src, DAG, Subtarget);
 
   SDValue VL = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget).second;
@@ -8882,6 +8892,8 @@ SDValue RISCVTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
   MVT XLenVT = Subtarget.getXLenVT();
   SDValue SplatZero = DAG.getConstant(0, DL, XLenVT);
   SDValue SplatTrueVal = DAG.getSignedConstant(ExtTrueVal, DL, XLenVT);
+  if (negated)
+    std::swap(SplatZero, SplatTrueVal);
 
   SplatZero = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT,
                           DAG.getUNDEF(ContainerVT), SplatZero, VL);