[llvm] Reduce shl64 to shl32 if shift range is [63-32] (PR #125574)

[Matt Arsenault via llvm-commits]

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@@ -4040,19 +4040,39 @@ SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(
 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
                                                 DAGCombinerInfo &DCI) const {
   EVT VT = N->getValueType(0);
+  SDValue LHS = N->getOperand(0);
+  SDValue RHS = N->getOperand(1);
+  ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS);
+  SDLoc SL(N);
+  SelectionDAG &DAG = DCI.DAG;
 
-  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
-  if (!RHS)
+  if (!CRHS) {
+    // shl i64 X, Y -> [0, shl i32 X, (Y & 0x1F)]
+    if (VT == MVT::i64) {
+      KnownBits Known = DAG.computeKnownBits(RHS);
+      EVT TargetType=VT.getHalfSizedIntegerVT(*DAG.getContext());
+      EVT TargetVecPairType=EVT::getVectorVT(*DAG.getContext(), TargetType, 2);
+
+      if (Known.getMinValue().getZExtValue() >= TargetType.getSizeInBits()) {
+        SDValue truncShiftAmt = DAG.getNode(ISD::TRUNCATE, SL, TargetType, RHS);
+        const SDValue ShiftMask = DAG.getConstant(TargetType.getSizeInBits() - 1, SL, TargetType);
+	// This AND instruction will be removed during later instruction selection.
+        SDValue MaskedShiftAmt =
+            DAG.getNode(ISD::AND, SL, TargetType, truncShiftAmt, ShiftMask);
+        SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, TargetType, LHS);
+        SDValue NewShift = DAG.getNode(ISD::SHL, SL, TargetType, Lo, MaskedShiftAmt);
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arsenm wrote:

This can preserve flags? https://alive2.llvm.org/ce/z/rehtsd

https://github.com/llvm/llvm-project/pull/125574