[llvm] [AMDGPU][LIT][NFC] Added xfail test for live-in CSR SGPR used partially (PR #126696)

[Vikash Gupta via llvm-commits]

https://github.com/vg0204 created https://github.com/llvm/llvm-project/pull/126696

None

>From 12c07f5a5ddec92aeb0da27f6cf7ef191e349360 Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Tue, 11 Feb 2025 08:13:39 +0000
Subject: [PATCH] [AMDGPU][LIT][NFC] Added xfail test for live-in CSR SGPR used
 partially

---
 .../spill-partial-csr-sgpr-live-ins.mir       | 52 +++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir

diff --git a/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir b/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
new file mode 100644
index 00000000000000..8ed88339d59181
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
@@ -0,0 +1,52 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s
+# XFAIL: *
+
+# FIXME : Currently, MRI's liveIn check for regiters does not take corresponding live-in's sub-registers in account. As a result
+# in SILowerSGPRSpills, the SubReg spill gets marked KILLED eventhough its SuperReg is in function Live-ins. This causes machine
+# verifier to now fail at direct usage of that SubReg, which intially should not be any problem before adding spill.
+
+# CHECK: *** Bad machine code: Using an undefined physical register ***
+
+---
+name: spill_partial_live_csr_sgpr_argument_test_1
+tracksRegLiveness: true
+liveins:
+  - { reg: '$sgpr50_sgpr51' }
+body:             |
+  bb.0:
+    liveins: $sgpr50_sgpr51
+
+    S_NOP 0, implicit $sgpr50
+    $sgpr50 = S_MOV_B32 0
+
+...
+
+---
+name: spill_partial_live_csr_sgpr_argument_test_2
+tracksRegLiveness: true
+liveins:
+  - { reg: '$sgpr50_sgpr51' }
+body:             |
+  bb.0:
+    liveins: $sgpr50_sgpr51
+
+    S_NOP 0, implicit $sgpr50
+    $sgpr50_sgpr51 = S_MOV_B64 0
+
+...
+
+---
+name: spill_partial_live_csr_sgpr_argument_test_3
+tracksRegLiveness: true
+liveins:
+  - { reg: '$sgpr52_sgpr53' }
+body:             |
+  bb.0:
+    liveins: $sgpr52_sgpr53
+
+    S_NOP 0, implicit $sgpr53
+    $sgpr52_sgpr53 = S_MOV_B64 0
+    $sgpr54 = S_MOV_B32 0
+
+...