[llvm] [AMDGPU][True16][CodeGen] build_vector pattern in true16 (PR #118904)

[Joe Nash via llvm-commits]

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@@ -3424,6 +3441,8 @@ def : GCNPat <
 
 // Take the upper 16 bits from V[0] and the lower 16 bits from V[1]
 // Special case, can use V_ALIGNBIT (always uses encoded literal)
+foreach p = [NotHasTrue16BitInsts, UseFakeTrue16Insts] in
+let True16Predicate = p in
 def : GCNPat <
   (vecTy (DivergentBinFrag<build_vector>
     (Ty !if(!eq(Ty, i16),
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Sisyph wrote:

Perhaps the PERM_B32 pat at new line 3456 should also be disabled in Real True16 mode? It seems redundant with the new REG_SEQUENCE  pat.

https://github.com/llvm/llvm-project/pull/118904