[llvm] [PPC] Implement `areInlineCompatible` (PR #126562)

[Henry Jiang via llvm-commits]

https://github.com/mustartt updated https://github.com/llvm/llvm-project/pull/126562

>From db41712e1f507ba8559a0472e92a2a1a4517f327 Mon Sep 17 00:00:00 2001
From: Henry Jiang <henry.jiang1 at ibm.com>
Date: Mon, 10 Feb 2025 13:03:59 -0500
Subject: [PATCH 1/2] Implement areInlineCompatible for PPC

---
 llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 14 ++++++++++++++
 llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h   |  2 ++
 2 files changed, 16 insertions(+)

diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index c308ec332e84434..26e9b4b9facec35 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -895,6 +895,20 @@ PPCTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
   return BaseT::getIntrinsicInstrCost(ICA, CostKind);
 }
 
+bool PPCTTIImpl::areInlineCompatible(const Function *Caller,
+                                     const Function *Callee) const {
+  const TargetMachine &TM = getTLI()->getTargetMachine();
+
+  const FeatureBitset &CallerBits =
+      TM.getSubtargetImpl(*Caller)->getFeatureBits();
+  const FeatureBitset &CalleeBits =
+      TM.getSubtargetImpl(*Callee)->getFeatureBits();
+
+  // Check that targets features are exactly the same. We can revisit to see if
+  // we can improve this.
+  return CallerBits == CalleeBits;
+}
+
 bool PPCTTIImpl::areTypesABICompatible(const Function *Caller,
                                        const Function *Callee,
                                        const ArrayRef<Type *> &Types) const {
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
index 3cb60d7a1785ae3..bf3ddad134e14c3 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
@@ -139,6 +139,8 @@ class PPCTTIImpl : public BasicTTIImplBase<PPCTTIImpl> {
       bool UseMaskForCond = false, bool UseMaskForGaps = false);
   InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
                                         TTI::TargetCostKind CostKind);
+  bool areInlineCompatible(const Function *Caller,
+                           const Function *Callee) const;
   bool areTypesABICompatible(const Function *Caller, const Function *Callee,
                              const ArrayRef<Type *> &Types) const;
   bool hasActiveVectorLength(unsigned Opcode, Type *DataType,

>From ad6127b6517bb403896de80a5cc540440f653d50 Mon Sep 17 00:00:00 2001
From: Henry Jiang <henry.jiang1 at ibm.com>
Date: Mon, 10 Feb 2025 15:27:00 -0500
Subject: [PATCH 2/2] add inline attr test

---
 .../Inline/PowerPC/inline-target-attr.ll      | 37 +++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll

diff --git a/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll b/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
new file mode 100644
index 000000000000000..ff11ca827023fe9
--- /dev/null
+++ b/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
@@ -0,0 +1,37 @@
+; RUN: opt < %s -mtriple=powerpc64le-ibm-linux-gnu -S -passes=inline | FileCheck %s
+; RUN: opt < %s -mtriple=powerpc64le-ibm-linux-gnu -S -passes='cgscc(inline)' | FileCheck %s
+
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64le-ibm-linux-gnu"
+
+declare i32 @inlined()
+
+define i32 @foo() #0 {
+; CHECK-LABEL: foo
+; CHECK: entry
+; CHECK-NEXT: call i32 @bar()
+; CHECK-NEXT: call i32 @inlined()
+entry:
+    %1 = call i32 @bar()
+    %2 = call i32 @baz()
+    %3 = add i32 %1, %2
+    ret i32 %3
+}
+
+define i32 @bar() #1 {
+entry:
+    %1 = call i32 @inlined()
+    ret i32 %1
+}
+
+define i32 @baz() #0 {
+entry:
+    %1 = call i32 @inlined()
+    ret i32 %1
+}
+
+attributes #0 = { "target-cpu"="pwr7" "target-features"="+allow-unaligned-fp-access" }
+
+; We explictly disable -power8-vector to avoid emitting those instructions
+; so we should not inline them into +power8-vector
+attributes #1 = { "target-cpu"="pwr7" "target-features"="-allow-unaligned-fp-access" }