[llvm] [RISCV][VLOPT] Add support for Vector Fixed-Point Arithmetic Instructions (PR #126483)

[Luke Lau via llvm-commits]

================
@@ -1173,8 +1201,16 @@ bool RISCVVLOptimizer::isCandidate(const MachineInstr &MI) const {
   const MCInstrDesc &Desc = MI.getDesc();
   if (!RISCVII::hasVLOp(Desc.TSFlags) || !RISCVII::hasSEWOp(Desc.TSFlags))
     return false;
-  if (MI.getNumDefs() != 1)
+
+  if (MI.getNumExplicitDefs() != 1)
+    return false;
+
+  // Some instructions have implicit defs e.g. $vxsat. If they might be read
----------------
lukel97 wrote:

e.g. if we have `vd = vsaddu.vi [0, 0, 0, 255], 1` for sew=e8, then at vl=4 `vxsat` would be set because the 3rd element would have been saturated.

If we reduce vl=3, then we don't perform the operation on it and it doesn't get saturated, so `vxsat` doesn't get set.

At least this is how I interpret the spec, it seems to be a bit vague here: 

> Saturating forms of integer add and subtract are provided, for both signed and unsigned integers. If
the result would overflow the destination, the result is replaced with the closest representable value,
and the vxsat bit is set.

I **presume** when it talks about the result, it means any active element. 

https://github.com/llvm/llvm-project/pull/126483