[llvm] 30e7c10 - [AMDGPU] - Fix non-deterministic compile issue (#126271)

[via llvm-commits]

Author: David Stuttard
Date: 2025-02-10T07:58:02Z
New Revision: 30e7c101465d5fa4e9266b9ae3b238eb8cf4533b

URL: https://github.com/llvm/llvm-project/commit/30e7c101465d5fa4e9266b9ae3b238eb8cf4533b
DIFF: https://github.com/llvm/llvm-project/commit/30e7c101465d5fa4e9266b9ae3b238eb8cf4533b.diff

LOG: [AMDGPU] - Fix non-deterministic compile issue (#126271)

4ce1f9079d4d3 [AMDGPU] Allow rematerialization of instructions with
virtual register uses (#124327)
made changes that require an ordered traversal of a DenseMap. Changing
it to MapVector which
respects insertion order.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/GCNSchedStrategy.h

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
index 7d3e63df43da60..e3da8d30056293 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
@@ -442,7 +442,7 @@ class PreRARematStage : public GCNSchedStage {
 
   // Map a trivially rematerializable def to a list of regions at MinOccupancy
   // that has the defined reg as a live-in.
-  DenseMap<MachineInstr *, SmallVector<unsigned, 4>> RematDefToLiveInRegions;
+  MapVector<MachineInstr *, SmallVector<unsigned, 4>> RematDefToLiveInRegions;
 
   // Collect all trivially rematerializable VGPR instructions with a single def
   // and single use outside the defining block into RematerializableInsts.