[llvm] [MachineScheduler][RISCV] Release the pending queue base on condition (PR #125468)

[Pengcheng Wang via llvm-commits]

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@@ -954,3 +966,47 @@ bool RISCVRegisterInfo::getRegAllocationHints(
 
   return BaseImplRetVal;
 }
+
+static bool isRVVPressureSetIdx(unsigned Idx) {
+  const static std::vector<unsigned> RVVPressureSetIndices = {
+      RISCV::RegisterPressureSets::VRM8NoV0, RISCV::RegisterPressureSets::VM};
+
+  return llvm::find(RVVPressureSetIndices, Idx) != RVVPressureSetIndices.end();
+}
+
+bool RISCVRegisterInfo::shouldReleasePendingQueue(
+    MachineFunction &MF, ArrayRef<unsigned> MaxSetPressure) const {
+
+  if (!MF.getSubtarget<RISCVSubtarget>().hasVInstructions())
+    return false;
+
+  for (unsigned Idx = 0; Idx < MaxSetPressure.size(); Idx++) {
+    // Consider only the RVV Register, as RVV spilling/reloading has higher
+    // potential costs than hazards.
+    if (!isRVVPressureSetIdx(Idx))
+      continue;
+    if (MaxSetPressure[Idx] + RVVReleasePendingPressureThreshold >
+        getRegPressureSetLimit(MF, Idx)) {
+      return true;
+    }
+  }
+  return false;
+}
+
+bool RISCVRegisterInfo::shouldReleaseSUFromPendingQueue(
+    MachineFunction &MF, ArrayRef<unsigned> PSetID,
+    ArrayRef<int> UnitInc) const {
+
+  if (!MF.getSubtarget<RISCVSubtarget>().hasVInstructions())
+    return false;
+
+  for (unsigned Idx = 0; Idx < PSetID.size(); Idx++) {
+    // Consider only the RVV Register, as RVV spilling/reloading has higher
+    // potential costs than hazards.
+    if (!isRVVPressureSetIdx(PSetID[Idx]))
+      continue;
+    if (UnitInc[Idx] < UnitIncRVVRegPressureThreshold)
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wangpc-pp wrote:

Does both TopDown and BottomUp have the same threshold? IIRC, they have different computations of register pressure so the threshold may be different?

https://github.com/llvm/llvm-project/pull/125468