[llvm] aebe6c5 - [RISCV] Improve Errors for X1/X5/X1X5 Reg Classes (#126184)

[via llvm-commits]

Author: Sam Elliott
Date: 2025-02-09T21:35:32-08:00
New Revision: aebe6c5d7f88a05a29ef6c643482ca7eaf994b19

URL: https://github.com/llvm/llvm-project/commit/aebe6c5d7f88a05a29ef6c643482ca7eaf994b19
DIFF: https://github.com/llvm/llvm-project/commit/aebe6c5d7f88a05a29ef6c643482ca7eaf994b19.diff

LOG: [RISCV] Improve Errors for X1/X5/X1X5 Reg Classes (#126184)

LLVM has functionality for producing a register-class-specific error
message in the assembly parser, rather than just emitting the generic
"invalid operand for instruction" error.

This starts the gradual adoption of this functionality for RISC-V, with
some lesser-used shadow-stack register classes:
- GPRX1 (only contains `ra`)
- GPRX5 (only contains `t0`)
- GPRX1X5 (only contains `ra` and `t0`)

LLVM is reasonably conservative about when these errors are used, in
particular you have to have all the features for the relevant mnemonic
enabled before it will do, hence the test updates.

This also merges a pair of almost identical rv32/rv64 test files into a
single file with one run line.

Added: 
    llvm/test/MC/RISCV/zicfiss-invalid.s

Modified: 
    llvm/lib/Target/RISCV/RISCVRegisterInfo.td

Removed: 
    llvm/test/MC/RISCV/rv32zicfiss-invalid.s
    llvm/test/MC/RISCV/rv64zicfiss-invalid.s


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 7eb93973459c0d3..e7e7a4b7d035bfd 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -247,8 +247,16 @@ def GPR : GPRRegisterClass<(add (sequence "X%u", 10, 17),
                                 (sequence "X%u", 0, 4))>;
 
 def GPRX0 : GPRRegisterClass<(add X0)>;
-def GPRX1 : GPRRegisterClass<(add X1)>;
-def GPRX5 : GPRRegisterClass<(add X5)>;
+
+def GPRX1 : GPRRegisterClass<(add X1)> {
+  let DiagnosticType = "InvalidRegClassGPRX1";
+  let DiagnosticString = "register must be ra (x1)";
+}
+
+def GPRX5 : GPRRegisterClass<(add X5)> {
+  let DiagnosticType = "InvalidRegClassGPRX5";
+  let DiagnosticString = "register must be t0 (x5)";
+}
 
 def GPRNoX0 : GPRRegisterClass<(sub GPR, X0)>;
 
@@ -282,7 +290,10 @@ def SP : GPRRegisterClass<(add X2)>;
 def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
                                  (sequence "X%u", 18, 23))>;
 
-def GPRX1X5 :  GPRRegisterClass<(add X1, X5)>;
+def GPRX1X5 :  GPRRegisterClass<(add X1, X5)> {
+  let DiagnosticType = "InvalidRegClassGPRX1X5";
+  let DiagnosticString = "register must be ra or t0 (x1 or x5)";
+}
 
 //===----------------------------------------------------------------------===//
 // Even-Odd GPR Pairs

diff  --git a/llvm/test/MC/RISCV/rv32zicfiss-invalid.s b/llvm/test/MC/RISCV/rv32zicfiss-invalid.s
deleted file mode 100644
index 048df67e8a6461b..000000000000000
--- a/llvm/test/MC/RISCV/rv32zicfiss-invalid.s
+++ /dev/null
@@ -1,17 +0,0 @@
-# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -M no-aliases -show-encoding \
-# RUN:     2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
-
-# CHECK-ERR: error: invalid operand for instruction
-sspopchk a1
-
-# CHECK-ERR: error: invalid operand for instruction
-c.sspush t0
-
-# CHECK-ERR: error: invalid operand for instruction
-c.sspopchk ra
-
-# CHECK-ERR: error: invalid operand for instruction
-sspush a0
-
-# CHECK-ERR: error: invalid operand for instruction
-ssrdp zero

diff  --git a/llvm/test/MC/RISCV/rv64zicfiss-invalid.s b/llvm/test/MC/RISCV/rv64zicfiss-invalid.s
deleted file mode 100644
index fc69c68a477d6cc..000000000000000
--- a/llvm/test/MC/RISCV/rv64zicfiss-invalid.s
+++ /dev/null
@@ -1,17 +0,0 @@
-# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -M no-aliases -show-encoding \
-# RUN:     2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
-
-# CHECK-ERR: error: invalid operand for instruction
-sspopchk a1
-
-# CHECK-ERR: error: invalid operand for instruction
-c.sspush t0
-
-# CHECK-ERR: error: invalid operand for instruction
-c.sspopchk ra
-
-# CHECK-ERR: error: invalid operand for instruction
-sspush a0
-
-# CHECK-ERR: error: invalid operand for instruction
-ssrdp zero

diff  --git a/llvm/test/MC/RISCV/zicfiss-invalid.s b/llvm/test/MC/RISCV/zicfiss-invalid.s
new file mode 100644
index 000000000000000..a5ab9240f3faddd
--- /dev/null
+++ b/llvm/test/MC/RISCV/zicfiss-invalid.s
@@ -0,0 +1,19 @@
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+zcmop,+c -M no-aliases -show-encoding \
+# RUN:     2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
+# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+zcmop,+c -M no-aliases -show-encoding \
+# RUN:     2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
+
+# CHECK-ERR: error: register must be ra or t0 (x1 or x5)
+sspopchk a1
+
+# CHECK-ERR: error: register must be ra (x1)
+c.sspush t0
+
+# CHECK-ERR: error: register must be t0 (x5)
+c.sspopchk ra
+
+# CHECK-ERR: error: register must be ra or t0 (x1 or x5)
+sspush a0
+
+# CHECK-ERR: error: invalid operand for instruction
+ssrdp zero